I was asked a question on how to reduce leakage for digital circuits. I started by detailing process options that effect leakage, each effective both leakage and circuit performance. In this article, I will detail two methods to reduce leakage while maintaining circuit performance. I assume that the circuit at hand requires the highest performance in some active mode but must greatly reduce its leakage in a standby mode. Continued…
Typical CMOS device/process options
I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let’s go over some process options that effect leakage. Continued…
Posted in Digital Professional.
Unity STF | A sigma-delta linearization method
In a previous post, I discussed the trade-offs in linearity of several continuous-time sigma-delta schemes. In this post, I will describe a method that linearizes the sigma-delta noise-shaping filter (NSF). That is, the scheme presented in this article greatly suppresses the linearity requirements on the noise-shaping filter. This method applies to both discrete-time and continuous-time sigma-delta ADC’s. However, it is more powerful with continuous-time sigma-delta because it enables the active-RC configuration.
Posted in Analog Professional.
Continuous time sigma-delta ADC noise shaping filter circuit architectures
The continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) is a class of sigma-delta analog-to-digital converters that utilize a continuous-time noise-shaping filter (NSF | H(s)). In this post, I analyze a few noise-shaping filter (NSF) architectures that affect highly linear CTSD ADC’s.
Posted in Analog Professional.
Circuit Simulator Analyses
I’ve decided to go through some basics of circuit design. In this post, I’ll cover the different types of circuit simulator analyses. Most are available in SPICE, Synopsys HSPICE, Cadence Spectre, and Agilent ADS, depending on vendor-specific options.
Posted in Analog Professional.
Supply voltage, current, RF impedance, and CMOS scaling
Consider the circuit below:
Let’s say that you’ve designed the circuit with a supply voltage (VDD) of 2.4 V. It’s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are:
PMOS: IDP×VDSATP = 10 mA×0.6 V
NMOS: IDN×VDSATN = 10 mA×1.2 V
You have 0.6 V of headroom at the output for signal swing.
The differential input impedance is 2/gm of the NMOS transistors:
Rin = 2/gmn = VDSATN / IDN = 1.2 V / 10 mA = 120 Ω
where we have the used the relation gm = 2×ID/VDSAT which excludes short-channel effects. Including short-channel effects changes the relationship, but won’t change the conclusion of this topic.
You need a balun anyway, so you have a transformer that steps up from 50 Ω to 120 Ω
Great. The product ships and it sells well.
Your boss/customer comes by and asks you for a next generation part. They want to simplify the power regulation scheme on their products, so they absolutely have to have a 1.2 V supply. There’s no negotiation on this supply voltage.
Posted in Analog Professional.
Fundamentals of Analog/RF design: Noise, Signal, Power
Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog/RF design: that to maintain a given SNR, a certain amount of power must be consumed by an analog/RF circuit.
Posted in Analog Professional.
The case for the trans-conducting LNA
In this post, I will show an evolution of a trans-conducting LNA (rather than a voltage-gain LNA). This is a prime example of current-mode circuit design, which has benefits in terms of linearity—especially for low-voltage scaling in RFCMOS design.
Posted in Analog Professional.