Comments on: Minimizing leakage for high-performance CMOS circuits http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/ Tutorials and Insights in Electronics and Circuit Design Wed, 07 Sep 2011 12:13:21 +0000 hourly 1 By: Friedel http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/comment-page-1/#comment-179 Friedel Tue, 16 Dec 2008 23:51:53 +0000 http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/#comment-179 Dear Poojan, I agree that reverse bias helped in the "good old days" of process nodes like 180nm. But if you simulate the bulk effect in e.g. 45nm, you will see that the 1000x Ids leakage reduction in 180nm will shrink to <10x best case in 45nm. On top of the Ids leakage, gate leakage gets more pronounced! Thanks Friedel Dear Poojan,

I agree that reverse bias helped in the “good old days” of process nodes like 180nm.
But if you simulate the bulk effect in e.g. 45nm, you will see that the 1000x Ids leakage reduction in 180nm will shrink to <10x best case in 45nm.
On top of the Ids leakage, gate leakage gets more pronounced!

Thanks
Friedel

]]> By: Poojan Wagh http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/comment-page-1/#comment-160 Poojan Wagh Fri, 05 Dec 2008 01:09:07 +0000 http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/#comment-160 @Bapcha Murty: I concur. I think the high-side switch is the way to go. However, there <em>are</em> some benefits of the reverse body bias. I just wanted to give as many options out there as possible for my readers and let them decide. Their decision, nonetheless, should be to just use a switch 90% of the time. Could you explain what you mean by increasing sidewall capacitance? @Bapcha Murty:
I concur. I think the high-side switch is the way to go. However, there are some benefits of the reverse body bias. I just wanted to give as many options out there as possible for my readers and let them decide. Their decision, nonetheless, should be to just use a switch 90% of the time.

Could you explain what you mean by increasing sidewall capacitance?

]]> By: Bapcha Murty http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/comment-page-1/#comment-159 Bapcha Murty Thu, 04 Dec 2008 23:10:54 +0000 http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/#comment-159 1. Reverse body bias will require that you do a custom layout to minimize the chances of latching up - plus, you will end up increasing CJSW [side-wall capacitance]. 2. Stacking devices - as in the supply switch circuit - will decrease DC power and standby power, but you need LARGE enable transistors to implement a high-speed circuit. Intuitively, I think that using the reverse body bias to eke out better performance is a bad engineering trade-off to make, while I'd be more comfortable with the switched power supply solution. Bapcha 1. Reverse body bias will require that you do a custom layout to minimize the chances of latching up – plus, you will end up increasing CJSW [side-wall capacitance].

2. Stacking devices – as in the supply switch circuit – will decrease DC power and standby power, but you need LARGE enable transistors to implement a high-speed circuit.

Intuitively, I think that using the reverse body bias to eke out better performance is a bad engineering trade-off to make, while I’d be more comfortable with the switched power supply solution.

Bapcha

]]> By: Minimizing leakage for high-performance CMOS circuits | Circuit Design http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/comment-page-1/#comment-153 Minimizing leakage for high-performance CMOS circuits | Circuit Design Wed, 03 Dec 2008 05:30:14 +0000 http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/#comment-153 [...] unknown wrote an interesting post today onHere’s a quick excerptMost recently, he is working in the areas of analog-to-digital converter design in […] Share and Enjoy: These icons link to social bookmarking sites where readers can share and discover new web pages. … [...] [...] unknown wrote an interesting post today onHere’s a quick excerptMost recently, he is working in the areas of analog-to-digital converter design in […] Share and Enjoy: These icons link to social bookmarking sites where readers can share and discover new web pages. … [...]

]]> By: Typical CMOS device/process options | Circuit Design http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/comment-page-1/#comment-152 Typical CMOS device/process options | Circuit Design Wed, 03 Dec 2008 04:34:48 +0000 http://www.circuitdesign.info/blog/2008/12/minimizing-leakage-for-high-performance-cmos-circuits/#comment-152 [...] Of course, each of these options have the implicit tradeoff of performance/speed at the expense of leakage. What do you do when you want performance during active operation and low leakage during a standby mode? I will detail two methods in a future article. [...] [...] Of course, each of these options have the implicit tradeoff of performance/speed at the expense of leakage. What do you do when you want performance during active operation and low leakage during a standby mode? I will detail two methods in a future article. [...]

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