Comments on: You want latches? We got latches | Flip-Flop Design

By: Nizamuddin

Nizamuddin — Thu, 01 Jan 2009 05:39:12 +0000

very good tutorial on cmos based latch design

By: Poojan Wagh

Poojan Wagh — Mon, 29 Dec 2008 04:06:01 +0000

@Graham Petley:
Hi, Graham. Your schematics look correct to me. As you stated, the real implementation benefit of this configuration is in a fully-differential configuration, where I get to divide the power in half (or to put it another way, where I’d have 2 single-ended latches anyway).

The other benefit of this design is that it has an evolution from the basic latch configuration, which serves as a good introduction to the workings of the latch.

I will admit that as an analog/RF engineer, I haven’t really strayed outside of these (or similar) latch designs, as a fully-differential topology is strongly preferred, due to lower clock-induced supply bounce. These designs favor 50% duty ratio outputs over power efficiency. Of course, the majority of people don’t care about duty ratio and matched rise/fall times.

I don’t claim that it’s an optimal general purpose latch–but it does its job at rather high frequencies.

By: Graham Petley

Graham Petley — Tue, 23 Dec 2008 12:23:11 +0000

This is an unusual D-flop design which I wasn’t familiar with. I wrote up a Spice deck and compared the perf with a regular D-flop design at http://www.vlsitechnology.org/html/cells/vsclib013/dfnt1.html. The new one is at http://www.vlsitechnology.org/html/cells/vsclib013/dfnt2.html.
In the case of single date and clock inputs and a single output, I can’t see the advantage of this design. It’s very big (34 transistors cf 24 for the regular flop) and uses more power for a slower speed. I also found bigger setup and hold times.
The parasitic caps are estimates since I haven’t drawn a layout. I think it will be complex, with the nodes n1p,n1n thru n5p.n5n being tricky because continuous diffusion isn’t possible.
Is the schematic I have drawn correct?

By: Robert Tso

Robert Tso — Sun, 21 Dec 2008 00:15:27 +0000

Very nice tutorial.

By: Poojan Wagh

Poojan Wagh — Sat, 20 Dec 2008 02:23:15 +0000

@mm: Thanks for the heads-up. I foud out that WordPress (or its Carrington theme) wasn’t rendering underlines (which I was using as a proxy for overbars). Luckily, with a web version of Latex, I a now able to represent both C & C-bar.

By: Poojan Wagh

Poojan Wagh — Mon, 15 Dec 2008 11:09:56 +0000

@mm: You are correct; I have C & C-bar reversed in the description. I'll fix it when I get a chance.

By: mm

mm — Mon, 15 Dec 2008 10:50:50 +0000

It looks to me as if clock phases driving PMOS devices in the pre-charge type circuit were reversed. To make the circuit work as described, first stage should be driven with “C” and the second one with “/C”.