Category Archives: Analog Professional

Posts that would interest electrical engineers proficient in analog circuit design.

Impulse Invariant Transform

Introduction The impulse invariant transform (IIT) is a method of taking a continuous-time system H(s) and converting it to a discrete-time system. There are multiple ways of doing this, but the IIT does so with the constraint that the impulse response of the discrete-time system is a sampled version of the impulse response of the [...]
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Non-Radix-2 FFT in Cadence/Ocean/Skill/Spectre | Using Cadence IPC to talk to Matlab (or anything else)

Introduction I had been working on a pulse-width-modulation (PWM) design. It was a pseudo-digital implementation, in that the output was clocked by a high-speed clock. The actual switching rate was much lower than this clock. I wanted to simulate this design in Cadence/Spectre by running a transient and then taking an FFT. However, I ran [...]
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The Viterbi Sigma-Delta (at CircuitSage)

I’ve posted a guest article at Circuit Sage, detailing the derivation of a “Viterbi” over-sampling data converter. I’m quite proud of this one. Go over and check it out. FYI: this is also the reason I didn’t post directly to this site this week. I try to do a post per week, but the article [...]
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Asymmetric chopping for improved IM3 | A dead-end research topic?

In my prior post, I discussed the use of “chopping” (or pre- and post-mixing) to improve the IM2 of RF/analog circuits. New readers should go back and read that post in order to understand the nomenclature and variable names in this post. Lately, I’ve been considering whether any similar (but different) technique can be used [...]
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Reader Round-Up (vol 1)

Answers question in I/Q Noise figure, and on how to do stability in Cadence ADE.
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Chopping to alleviate IM2,

IM2 Consider the fully differential amplifier shown below:
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MOS Diffusion Parasitics

I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance.
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Unity STF | A sigma-delta linearization method

In a previous post, I discussed the trade-offs in linearity of several continuous-time sigma-delta schemes. In this post, I will describe a method that linearizes the sigma-delta noise-shaping filter (NSF). That is, the scheme presented in this article greatly suppresses the linearity requirements on the noise-shaping filter. This method applies to both discrete-time and continuous-time [...]
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