Comments for Circuit Design

Comment on Asymmetric chopping for improved IM3 | A dead-end research topic? by Asymmetric chopping for improved IM3 | A dead-end research topic …

Asymmetric chopping for improved IM3 | A dead-end research topic … — Mon, 05 Jan 2009 07:52:33 +0000

[...] unknown wrote an interesting post today onHere’s a quick excerptMost recently, he is working in the areas of analog-to-digital converter design in […] Share and Enjoy: These icons link to social bookmarking sites where readers can share and discover new web pages. … [...]

Comment on Chopping to alleviate IM2, by Asymmetric chopping for improved IM3 | A dead-end research topic? | Circuit Design

Mon, 05 Jan 2009 05:16:46 +0000

[...] my prior post, I discussed the use of "chopping" (or pre- and post-mixing) to improve the IM2 of [...]

Comment on You want latches? We got latches | Flip-Flop Design by Nizamuddin

Nizamuddin — Thu, 01 Jan 2009 05:39:12 +0000

very good tutorial on cmos based latch design

Comment on You want latches? We got latches | Flip-Flop Design by Poojan Wagh

Poojan Wagh — Mon, 29 Dec 2008 04:06:01 +0000

@Graham Petley:
Hi, Graham. Your schematics look correct to me. As you stated, the real implementation benefit of this configuration is in a fully-differential configuration, where I get to divide the power in half (or to put it another way, where I’d have 2 single-ended latches anyway).

The other benefit of this design is that it has an evolution from the basic latch configuration, which serves as a good introduction to the workings of the latch.

I will admit that as an analog/RF engineer, I haven’t really strayed outside of these (or similar) latch designs, as a fully-differential topology is strongly preferred, due to lower clock-induced supply bounce. These designs favor 50% duty ratio outputs over power efficiency. Of course, the majority of people don’t care about duty ratio and matched rise/fall times.

I don’t claim that it’s an optimal general purpose latch–but it does its job at rather high frequencies.

Comment on The case for the trans-conducting LNA by Poojan Wagh

Poojan Wagh — Mon, 29 Dec 2008 03:22:43 +0000

@Robert Tso:

You’re right about the impedance going high outside of the gain-bandwidth of the op-amp. Typically, you’ll want to put a capacitor on the inputs of the PMA to maintain a low impedance when the PMA’s op-amp (OTA) runs out of steam (and to suck out any LO injection). The addition of such a capacitor is not trivial as it can really screw up stability.

I also recall that there’s a filter configuration (was it Tow-Thomas?) that includes such a capacitor.

I will admit ignorance on many of the details of the BBF, because there was either someone else to do that job (which, I will admit, is the crux of this configuration), or I was always pulled off to other tasks.

Comment on The case for the trans-conducting LNA by Robert Tso

Robert Tso — Wed, 24 Dec 2008 20:06:17 +0000

If the post mixer amplifier is a low bandwidth amplifier, then it will not do a very good job in presenting a low impedance at the mixer output or at the gm stage output, - so the benefits of improving gm stage linearity would not be realized
The likely advantage of the 2nd schematic configuration is that it allows a filter to be placed between the mixer and baseband amp.

Comment on Chopping to alleviate IM2, by Poojan Wagh

Poojan Wagh — Wed, 24 Dec 2008 18:42:41 +0000

@Robert Tso: You’re absolutely right. I fixed it. The coefficients of x () should not have changed. Thanks Robert! Good eye!

Comment on Chopping to alleviate IM2, by Robert Tso

Robert Tso — Wed, 24 Dec 2008 18:13:38 +0000

Sorry, but b1 and b2 are the coefficients for the x^2 term, but in the last two equations they suddenly became coefficients for the x^3 term, simply by multiplying by p again. Is this correct? It would seem to me the magnitude is still determined by x^2, but the frequency is shifted by p^3.

Comment on You want latches? We got latches | Flip-Flop Design by Graham Petley

Graham Petley — Tue, 23 Dec 2008 12:23:11 +0000

This is an unusual D-flop design which I wasn’t familiar with. I wrote up a Spice deck and compared the perf with a regular D-flop design at http://www.vlsitechnology.org/html/cells/vsclib013/dfnt1.html. The new one is at http://www.vlsitechnology.org/html/cells/vsclib013/dfnt2.html.
In the case of single date and clock inputs and a single output, I can’t see the advantage of this design. It’s very big (34 transistors cf 24 for the regular flop) and uses more power for a slower speed. I also found bigger setup and hold times.
The parasitic caps are estimates since I haven’t drawn a layout. I think it will be complex, with the nodes n1p,n1n thru n5p.n5n being tricky because continuous diffusion isn’t possible.
Is the schematic I have drawn correct?

Comment on You want latches? We got latches | Flip-Flop Design by Robert Tso

Robert Tso — Sun, 21 Dec 2008 00:15:27 +0000

Very nice tutorial.