Lately, I’ve been considering whether any similar (but different) technique can be used to improve IM3. I went through a few thought experiments and eventually concluded that it couldn’t be done. Nonetheless, I was quite proud of the journey and thought it was worth sharing. I also hope that someone else will use the ideas presented here to come up with something better. (This hope is true of everything I publish here.)

In short, it’s good to celebrate your achievements and document your failures. This post is a case of the latter.

IM3

Deviating from my prior post, I will not bother to break down the circuit into two sides of a fully-differential circuit. In the case of IM3, there is no difference between a single-ended and a fully-differential circuit (at least not mathematically). So, I’ll just assume that everything is fully differential (without loss of generality).

Let’s consider the IM3 component from our chopping system presented in the previous post:

This represents the usual polynomial model (up to the 3rd order) of a circuit. Let’s now consider how our IM2 chopping system does with respect to IM3:

In our conventional IM2-chopping system, . So, this means that the IM3 term –that is, this symmetric chopping does absolutely nothing for IM3. In fact, any sequence which obeys won’t work, because will equal 1.

Symmetric vs Asymmetric

I’m coining the term symmetric chopping and asymmetric chopping by borrowing phrases from cryptogrophy. A symmetric cipher is one that uses the same key to both encrypt and decrypt. Similarly, I’m defining a symmetric chopper as one that uses the same chopping sequence to both chop and anti-chop. An asymmetric cipher uses one key to encrypt and another to decrypt. I similarly define an asymmetric chopper as one that uses one sequence to chop and another signal to anti-chop. The necessary conditions are so that we can recover the desired linear component, and because that’s the trivial case of the symmetric chopper.

We must remove constraint , because otherwise when , and when , to meet the constraint that . We have to reject this trivial case because is not an asymmetric chopper–it is identical to the symmetrical chopper but we have introduced the redundant variable to describe it.

To recap, we’ve found that we can’t make a chopper with the property and have it improve IM3. The reason for this is that a term appears due to the IM3 of the circuit (which we are trying to linearize) and our symmetric anti-chopper multiplied again by to form .

Asymmetric Chopping

However, what if we consider the asymmetric chopper. Then, our output will be:

which, using the relation :

So, we now want a system where is a broadband (or out-of-band) signal. How do we generate such a signal? Well, let’s consider the 3-level case. We can consider , but we have to reject it because then when . In other words, we can’t have because then we can’t recover our signal. [In actuality, there may be a way to do exactly this, but I'll leave that option for a future post. I still have to work out the details.]

So, let’s now consider the case where and . [This case has the property that the dc value of is non-zero, . We'll set that fact aside for now.] Let’s call the associated values of as . What does this look like in the frequency domain? Well, we can express and as:

in other words:

which means that has a dc value of plus a broadband/out-of-band component :

In addition, the average power of is . Since it’s pointless to ascribe any gain or loss to the chopping function (since this can be mathematically ascribed to the gain coefficients of y), we can without loss of generality constrain the average power of to be 1:

So, for example, if , then .

Recall our result of asymmetric chopping:

So, the fundamental question is what does look like? Well, if , then . This can be represented as:

So, unfortunately, has a dc value of 1 and a broadband/modulated component:

As a result, asymmetric chopping cannot really suppress the IM3 term.

Even more anti-reasons

From the derivation above, I don’t believe that allowing to have more than two possible values will help. For exammple:

Since , the average value of will always be non-zero, and therefore there will always be some IM3 term blowing through.

Even if asymmetric chopping did fix the IM3 problem, there are practical difficulties with the system: for one, the chopper is no longer a switch-mode mixer (it is no longer selectively negating its input). As a result, one would have to worry about the linearity of the chopper itself. The same applies to the anti-chopper. (Although in an ADC or in a DAC, one would be able to implement one of the chopper/anti-chopper digitally and avoid one of them.)

If time avails, I will pursue the case of allowing some more and share my ideas on the subject in a separate post. In the meantime, your ideas and concerns are welcome. Consider the comment bubble to the lower right. Also, consider a subscription by email or RSS.

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2008-12-28 Update

I misread the email; the initial version of the I/Q noise figure discussion was completely wrong.

I/Q Noise Figure

What’s the difference of noise figure between quadrature [downconverter] and single downconverter? In the quadrature downconverter, you have I and Q path, if required Nf=10dB for this quadrature downconverter, what’s the Nf for the path of I or Q? Can I see the Nf for RF to I path is 7dB, the same thing for Q?

– K. C.

The answer is no. The important thing to remember when computing things in dB (and summing them) is whether they add in-phase (constructively) or not. Since the I and Q signals are completely orthogonal, if a 10 dB NF is required for the quadrature downconverter (I + jQ), then 10 dB is required for the each of the I and Q paths.

If, however, we had two paths that summed constructively, and we needed a 10 dB overall noise figure, then yes, each path would only need to deliver 13 dB (per path). Unfortunately, I and Q don’t do this constructive summation.

Loop gain in Cadence ADE

Can u please elaborate on loop gain/Stablity simulation using Cadence ADE?

– H. M.

Unfortunately, the answer is no. Or sort of. Sure, I can elaborate, but I can’t do a very good step-by-step job because I don’t have access to Cadence ADE. So, I’m running on my own memory, which (as my friends know) is very dangerous.

However, here’s a rough step-by-step:

1. Break the loop by inserting an Iprobe element. (Usually, I choose an Iprobe). You usually want to break the loop in a point that’s high-impedance. Typically, I choose the highest impedance output node (transconductor) looking into a compensation capacitor. So, the Iprobe would measure current going from the transconductor into its compensation capacitor.
2. Start ADE (Tools –> Analog Environment). If it’s not already set in the ADE window, select Setup (?) –> Simulator/Directory/Host and select spectre.
3. Select Setup –> Analysis and select stb (stability). You’ll need to select start and stop frequencies. There’s also a button to select the loop gain element (Iprobe) that you’re using to break the loop. (You can have multiple Iprobes in a single schematic, for each loop you want to analyze.)
4. After you run it, you can choose Outputs –> Plot –> Loop Gain (?) or something like that to see amplitude and phase vs frequency. You can also choose the loopgain result from the results browser and do a direct phaseMargin() measurement on it, which will pick the phase margin. (Something like phaseMargin(-getData(‘loopgain’ ?result ‘stb’)) – but I’m typing from memory.)
5. Keep in mind that Cadence returns the exact loop gain, which is (or should be) 180 degrees at dc. However, the phaseMargin() function expects the loop gain to be 0 degrees at dc and then go to 180 (unstable) at some point later. So, you have to invert the result when using phaseMargin().

The stability analysis, I believe, uses the Middlebrook method,which really runs two ac analyses and combines the results to produce the return ratio. Most other circuit simulators (HSPICE RF) have a similar capability. If your simulator doesn’t, it is possible to get the equivalent by manually running the two analyses.

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Consider the fully differential amplifier shown below:

is one side of the differential output and is the other. The fully differential output is . Without loss of generality, I have assumed infinite common-mode rejection . If we do the usual small-signal, polynomial expansion for and , we get:

This term, basically comes down to the mismatch in the two paths. If the two sides of the amplifier match completely, there will be no IM2. So, good matching reduces IM2, but it does not completely erradicate it.

Why is this important? After all, if (i.e. a sinusoid at input frequency :

The IM2 term is

The problem is that the dc term (if the amplifier is driving a mixer) can blow right through the mixer. Any mismatch in the mixer (including duty ratio errors in its LO) will allow the dc term through and stomp on the desired baseband signal.

Chopping

Now, consider if we insert two “chopping” mixers, each driven by a signal , in the chain:

We have and . Since the chopper is a switch-mode mixer, it can only pass or negate the inputs, so and therefore . Now, we have:

Finally, the post-chopper multiplies by again:

The term equals one:

The term has 3x the frequency content of and can generally be placed out of band.

Caveats

One problem with the system is that the finite-bandwidth amplifier between the pre- and post- choppers adds delay to the signal. This delay needs to be tracked by the pre-mixer LO and post-mixer LO. Otherwise, the two mixers won’t align and we won’t exactly get ; instead, we’ll get which gives us a little glitch (depending on how bad the delay is). This glitch yields a tone at the same frequency (and harmonics) of . In some cases, this frequency can mix out-of-band signals back in band–which defeats the purpose of improving IM2.

Spread Spectrum

Of course, there’s no reason that the needs to be tonal. It can, in fact, be made a spread-spectrum signal (for example, from a pseudo-noise (PN) sequence generator). In this case, the misalignment in delays will still yield bleed-through of . However, in this case, the misalignment won’t yield a tone; it will be a spread-spectrum signal which might not be as intrusive as a single tone.

The disadvantage is that the term won’t be so much shifted out of band as it will instead be spread to a wider bandwidth. Filtering will reduce some of the IM2 component, but it will not all be placed out of band.

Of course, one could combine the tonal and spread-spectrum qualities by composing with both a modulated and a spread-spectrum signal:

where is a pulse sequence and is a pseudo-noise sequence. This composition has the benefit of being both spread spectrum and out-of-band (modulated to a higher frequency).

IM3?

I’ve also been toying with the idea of whether such a system can be extended to improve IM3. I’ve concluded that it can–but not as effectively, and at the cost of some SNR. I will post the half-baked idea in the future. Perhaps someone (smarter than I) can build on the idea or will be inspired to build a better IM3 trap.

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Update 2008-12-19

This post probably didn’t make sense to many of you. I was representing C-bar (negation of C) by an underline. Unfortunately, WordPress (or maybe my theme) wasn’t rendering this underline, so didn’t look any different from . I’ve (obviously) rectified this ambiguity through the magic of Latex. If there are any errors now, they are solely my fault. (Let me know.)

Consider the cross-coupled inverters shown below:

The two inverters chasing their tail to the right of the input inverters represent a memory unit (i.e. a latch). When one output is high the other one is forced low. This low output then reinforces the first output being high. These two inverters form a positive feedback system.

I will represent almost all circuits as fully differential. That is generally how I’ve encountered these structures, and it also more general. If one wants a single-ended version, simply lop off one of the input structures (but keep the cross-coupled inverters).

This system has two stable states: the top output high (at supply) and the bottom output low (at ground) or vice versa. One additional trait of these cross-coupled inverters is that it takes a bit of effort to flip them from one state to the other. One must essentially cause the top output to go from high to low by overcoming the inverter driving the top output. In other words, the input inverters (on the left) must be sized larger than the cross-coupled inverters.

Our desire, however, is not to have the state change at random. We want the latch state to change only upon the transition of an external clock. This can easily be accomplished by passing the input inverter’s output through a transmission gate controlled by the clocks and .

Now, we have a true latch. I won’t repeat Wikipedia in analyzing a flip-flop as two successive latches triggered on opposite phases of the clock signal.

Now, let’s look closer at the inverter and T-gate combination in more detail:

The PMOS controlled by does very little when the output of the inverter is low. It is basically there for pull up. Similarly, when the inverter output is high, the NMOS controlled by does very little; it is basically there to pull low. As a result, we can lose the connections between the PMOS and NMOS in the T-gate and incorporate the T-gate into the inverter:

This structure has the advantage of allowing an contactless diffusion between the series PMOS devices and another contactless diffusion between the series NMOS devices, as I illustrated in the MOS diffusion parasitics article.

Another manipulation we can perform on this structure is to reverse the roles of input gates and clock gates (switching the connections of / and /):

Note that while both PMOS clock devices (driven by ) are turned on, only one is actively pulling up an output. For example, the PMOS devices on the left pulls up when is low. However, the upper right PMOS device (driven by ) does nothing because the PMOS in series with it is off ( is high).

I will draw this structure as a gated inverter in the future:

Up to this point, the input structure has always had to fight the memory effect of the cross-coupled inverters. Essentially, the input structure must inject enough current into the cross-coupled inverters to force them to switch states. This contention can result in considerable power draw. This power draw can be alleviated by gating the cross-coupled inverters (enabled on the opposite phase than that of the input structures):

Finally, the PMOS clock devices  can be combined into one device; and the NMOS clock devices (driven by ) can be combined into one device. I have omitted the cross-coupled inverter devices for brevity:

Doing so has the benefit the PMOS clock device can be twice as large while maintaining the same capacitive load on . Similarly, the NMOS clock signal can see the sum of the device widths from the previous configuration yet whichever NMOS is on ( or ) is now in series with a device twice as wide.

Finally, one can omit some level of gating by pre-charging the latch. That is, instead of waiting for the input to determine whether we pull the output high or not, we pull the output high during the first half of every cycle. During the second half, we pull down only if the input should really be low. The following flip-flop structure achieves this pre-charging. Once again, I have omitted the cross-coupled structures:

The first stage’s PMOS pulls up whenever is low on every cycle. Then, on the next half-cycle (when is high) the NMOS pulls down only when is high. Since the first stage only has one PMOS device (rather than two in series), the pull-up action is faster. Since we want to clock the second latch stage on the opposite phase (to form a full flip-flop), we need to invert the pre-charge and pre-charge low (rather than high).

The main problem with the pre-charge architecture as shown is that the first stage (for example) pulls up on every cycle even when the input is always high (and the output should be low). This represent a great deal of charging and discharging on the output of the first stage and thus dissipates power. However, this represents a fundamental trade-off: that one can gain increased speed at the expense of power.

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First, here’s the schematic for an inverter and an associated diagram of the wafer structure. The wafer is drawn vertically to match the schematic:

The upper p+, gate and p+ form the PMOS device. The lower n+, gate and n+ form the NMOS device. The p+ and n+ diffusions in the center are tied together to form the output node. The gates of the devices are tied together to form the input node. Of course, this diagram of diffusions is a simplification. A more detailed diagram is shown below, with body (back-gate/bulk) connections shown:

This diagram is of a dual-well process. I am not considering the triple-well case for this discussion, since isolation isn’t the topic of this article. In this case, I have tied the body of the NMOS device (substrate) to ground (VSS), and the body of the PMOS device (N-Well) to supply (VDD). Each of these diffusions (p+ or n+) yield a diode between their respective nodes and the body connection.

Since the NMOS source is connected to VSS, and the body is also connected to VSS, this diode is shorted (anode and cathode both connected to VSS). Similarly, since the PMOS source is connected to VDD, and the body is also connected to VDD, this diode is shorted (anode and cathode both connected to VDD). In short, no signal travels through the source nodes of either device; the source node does not move and its diode is essentially irrelevant. Consequently, the equivalent circuit model can exclude these devices:

I have explicitly drawn the drain diffusion diodes. The novice circuit designer should beware that these diodes are typically contained in the MOS models and do not explicitly need to be added—although their parameters (area, perimeter) would need to be specified for accurate simulation.

Our final step is to consider the geometric effect of these diffusion areas. I have shown a single p+ diffusion enlarged below:

It is essentially a cube of p+ in the N-Well. There is a diode junction on every surface of this cube except the top:

• The bottom of the cube has a diode area proportional to the width W length SD of the diffusion.
• The front and back walls of this cube have a diode area proportional to HD and SD
• The left and right walls have a diode area proportional to W and HD.

Now, imagine that this diffusion is the drain diffusion of a PMOS device. Imagine that the gate of the PMOS device is to the left of this diffusion. Then, the left sidewall doesn’t really have a diode to the body; it is instead modeled by the MOS device itself.

Typically, to specify this parasitic on a MOS model, one would specify the drain area (W x SD) and the perimeter (2xSD + W). From the perimiter, the sidewall area is computed automatically, since HD is a process parameter and does not vary from FET to FET.

The optimization becomes minimizing the area and perimeter for a given width W of FET. Consider the following FET:

It has a drain diffusion area of W & SD and a perimeter of 2SD + W, where SD is a design-rule parameter giving the minimum distance from gate edge to diffusion edge with enough space for a contact in the diffusion. If, instead, we share diffusions between two FET gates (by splitting up one device into two), we greatly reduce the perimeter and area per device width:

For the same total width W, we get an area of W/2 x SD and a perimeter of just 2 x SD. One should note that the SD is once again the minimum diffusion length that can accommodate a contact. In some cases, the contact is not necessary. For example, in the case of a cascode, one can share a diffusion without placing a contact—since the shared diffusion does not need to be routed elsewhere:

Finally, in older processes, it may be possible to implement a “circular FET”:

This configuration has no perimeter (side-wall) capacitance on the drain diffusion, at the cost of perhaps slightly larger area (bottom surface) capacitance. Unfortunately, in modern processes, the geometries are so fine that the corners tend to be an issue: although they appear to have 45° angles, the inner corner tends to curve inward and form a true circle. This inward growth of the gate causes the effective gate length to suffer (larger gate length). Instead of having a 20% faster FET (simulations without the curved interior gate), one can see a 20% slower FET (actual on-silicon performance).

In the next post, I will show some flip-flop designs. Cosider a subscription via RSS or via email.

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Supply Switch

The simplest method to reduce leakage in standby is to provide a switch to supply that opens during standby. Since the sea of digital devices are then disconnected from supply, their gates cannot be at supply and therefore their gate leakage goes away. In this case, I have represented the sea of gates as an inverter, with its supply and ground connections explicitly shown:

The bigger concern is active operation. The PMOS switch has some finite on-resistance. Current spikes during the transition of the digital circuits will cause voltage spikes on the supply of the digital circuit as Ohmic loss builds through the PMOS switch. In effect, the PMOS switch reduces the pull-up capability of every gate in the digital circuitry:

This transient supply droop can be alleviated by sufficient bypassing. The problem and solution follow identically my previous post on supply regulation except that in that case of a feedback regulator, the low on-resistance is more frequency-dependent than with the PMOS switch. To keep the static supply droop under control, the PMOS switch should be made adequately wide. Doing so can cause the supply switch to have a size on the order of the entire digital circuit area.

Reverse Body Bias

The back-gate or body can also be used to reduce leakage. Essentially, leakage gets reduced when the threshold is increased—decreased (increased in magnitude) for PMOS devices. Biasing the body below the source for NMOS or above the source for PMOS can increase the magnitude of the threshold voltage.

To do so, we allow two connections for the body. I have picked the PMOS case for the body switching because typically, there is one ground available but two supplies (a higher-voltage I/O supply and a lower-voltage core supply):

When the enable EN signal is asserted high, EN will be low and therefore turn on the PMOS device that ties the body of the core circuit’s PMOS device to VDDCORE. When EN is deasserted low, EN will be pulled high and turn off this connection. In its place, the secondary PMOS device will pull the core body connection to VDDIO, effectively increasing the magnitude of the Vt of the core PMOS device, and thus reducing leakage in the inverter.

The main difficulty with the above technique is that it requires a separate connection for the PMOS body. Typically, in standard cell logic, the body is directly connected to supply.

There is also a risk that if these body-connecting PMOS devices have too large of an on-resistance, they can cause latch-up. Care should be taken to ensure that the on-resistances of these deices are low. However, the size of the resulting PMOS devices in this case would still be much less than that required of an equivalent PMOS supply switch.

One of the main benefits of the reverse body bias technique is that it allows for circuits which hold state (static memory cells). This is out of my range of experience, but it may also improve the required refresh rates on dynamic memory cells, too—thus slowing down refresh clock rates and therefore greatly reducing power.

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Core Devices

Typically, foundries offer a few variations of there processes. I will call them general purpose (GP) and low power (LP). They differ in what I call the core devices, after which a process is usually named—for example, CMOS090 (90 nm) or TSMC 0.18μm.

GP

The GP represents the state of the art and usually drives large digital IC’s, including general purpose microprocessors and DSP’s. The traits of the GP process are a lower threshold and supply voltage, and possibly smaller effective gate length.

LP

The LP is usually a variant of the GP process optimized to reduce leakage (at the expense of speed). The LP option is usually used for highly integrated analog & RF CMOS IC’s, such as radios (RF transceivers), ADC’s, etc. Typically, the LP allows for a slightly higher supply voltage and sometimes has a slightly larger effective gate length. However, the main trait of the LP process is that the threshold is increased a bit from the GP process to allow for lower leakage. I’m not entirely sure if the higher supply voltage and gate length are intentional or are a byproduct of the higher threshold.

I/O Devices

Almost universally, all modern processes offer an “I/O” device. This is essentially a device from a prior process node (1.8 V, 2.5 V, or 3.3 V) with a larger gate length (0.18 um, 0.25 um, or 0.35 um). They are provided from a digital perspective as devices for pad drivers etc. However, they usually form the workhorse of analog/RF IC’s especially at baseband.

Device options

In both the GP and LP flavors, there are additional device options not necessarily universally, but usually:

• High-Vt: a core device with the threshold increased for lower leakage. This is also useful for larger output range on a diff pair—which depends on the input devices’ Vt—but usually an I/O device is even better.
• Low-Vt: a core device with the threshold decreased for higher performance (at the expense of leakage)
• Zero-Vt: a core device with a zero threshold voltage. This is useful for bypass switches and source followers.

These devices usually require additional mask steps and therefore incur additional processing costs.

Leakage

Basically, to minimize leakage, one should use the device with the highest threshold voltage that gets the job done. In order of preference:

1. I/O Device
2. High-Vt core device (if it is already available or if the expense makes sense)
3. Core (medium-Vt) devices

Of course, each of these options have the implicit tradeoff of performance/speed at the expense of leakage. What do you do when you want performance during active operation and low leakage during a standby mode? I will detail two methods in a future article.

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Band-limited STF

Consider the conventional sigma-delta architecture shown below:

I have shown it with one feedback path from the quantized output back to the input. However, the same result holds true if multiple feedback paths are provided.

Typically, the quantizer is modeled as an additive noise term N:

The response due to the input X and this additive quantization noise N is:

Thus, the signal-transfer function (STF) is H/(1+H) and the noise-transfer function (NTF) is 1/(1+H). The signal transfer function to the point Z is also H/(1+H).

I informally call this a band-limited STF since the signal-transfer function is band-limited by H: when H is low (there is no gain in the noise-shaping filter), the term H/(1+H) is also low. As a result, H/(1+H) follows approximately the same roll-off characteristics as H:

The noise-shaping filter H operates on the term X – Y which equals:

As one can see, this term includes both a signal component [X/(1+H)] and a noise component [N/(1+H)].

Unity STF

Consider instead what happens when we feed forward a signal term right before the quantizer:

Once again, modeling the quantizer as an additive noise N:

We find that the transfer terms are:

That is the STF is one for all frequencies (unity)—thus my nomenclature for this topology. The NTF remains unchanged. The STF to the point Z is also one for all frequencies.

Let’s now consider what the input to H looks like:

That is, the noise-shaping filter operates on a term that only depends on the additive noise. It is no longer signal dependent (at least not directly).

How does this improve the linearity requirements on the noise-shaping filter? Well, since the noise-shaping filter isn’t processing the input signal, it cannot have terms related to the input signal (x², x³, etc). Of course, this assumes N is not correlated with the input–N is white.

In reality, N will be dependent on the the input X, since N originates from quantization and a strong component of X appears at the quantizer. However, whatever N’s dependence on the input, it is less than X itself. As a result, the linearity requirements on the noise-shaping filter have been reduced (although not completely eradicated).

Implementation

One easy way to implement the unity STF structure is with an active-RC. We basically add an extra feedback resistor R2 (mistakenly labeled R1 in parallel with C2 in the picture) to the first stage of the active-RC structure that I discussed previously:

This causes not just an integral of the input, but a proportion of the input itself to pass through to the output of the filter.

Trade-Off’s

The main trade-off of this Unity STF method is that it relieves the requirements on the noise-shaping filter. However, for the quantizer, the requirements are worse.

With the band-limited STF, the quantizer saw a signal term with a gain of H/(1+H). With the unity STF method, the signal term at the input of the quantizer is unity. As a result, there is no roll-off and the entire signal (including all out-of-band interference terms) hit the quantizer right at its input. I’ll explain in a future post the exact nature of this problem as it applies to radio receivers.

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Reference

This idea (or at least my first encounter with it) appeared in “Wideband low-distortion delta-sigma ADC topology” by J. Silva, U. Moon, J. Steensgaard and G.C. Temes. ELECTRONICS LETTERS 7th June 2001 Vol. 37 No. 12. pp 737-738.

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The alternative sigma-delta ADC, the discrete-time sigma-delta (DTSD) employs switched-capacitor circuits that require op-amp bandwidths larger than the sampling rate and suffer from kT/C noise. In addition, discrete-time sigma-deltas require anti-alias filtering ahead of the ADC, whereas continuous-time sigma-deltas have built-in anti-aliasing. Specifically, aliasing occurs at the quantizer, which is within the sigma-delta loop (akin to quantization noise) and is therefore rejected by the loop.

The continuous-time sigma-delta loop is illustrated below:

Note that H(s) is a continuous-time filter (s-domain) and there is a DAC in the feedback path to convert from digital back to analog. The comparator shown is a clocked comparator, producing a digital word Y (N-bit).

This article will focus on the choice of architectures for H(s). I will assume the following 3rd-order topology for H(s):

A series of integrators are cascaded and then summed (with weightings k1, k2, and k3) to produce the input z to the comparator.  This filter implements

(K₁s² + K₂s + K₃)/s³

Often times, a noise-transfer zero is desired (to widen the noise-shaped bandwidth); this can be accommodated with the following:

The feedback term γ/s creates a (resonant) pole in the noise-shaping filter which maps to an imaginary zero in the noise transfer function (NTF).

Typically, the active-RC configuration is used for continuous-time filters that are to be tightly controlled and where high linearity is necessary. The first integrator (for example) is composed of a stage shown below:

The analog input voltage is converted to a current. Likewise, the DAC feedback voltage is converted to a current. These currents are subtracted into the summing junction and integrated on the capacitor C.

Unfortunately, the main disadvantage of this topology is that the op-amp must now source and sink the DAC current pulse. The response of the op-amp creates an inter-symbol interference problem. The integrated current follows the pulse response of the op-amp. However, when three positive pulses are generated from the DAC, their integrated value does not equal the integrated value of a +1, –1, and +1 sequence of pulses:

A +1, -1, +1 sequence results in an integrated value of +0.6-0.6+0.6 = 0.6 …

… whereas a +1, +1, +1 sequence results in an integrated value of +0.6+1.0+1.0 = 2.6

In short, the op-amp has an easier time with the DAC maintains a constant output than when it transitions. As a result, the integrated value is signal-dependent, which means it is nonlinear. This effect is worse when the op-amp slews, but occurs even when the op-amp operates in a linear manner.

A popular alternative to the active-RC is the Gm-C architecture:

In this case, a (current-mode) DAC’s output is directly summed with the signal current onto an integrated capacitor (which I thoughtfully forgot to draw in the illustration). This architecture isolates the DAC signal from the analog input signal. Consequently, the transconductor requirements are greatly relaxed; it only needs to tolerate the DAC switching on its output, but does not need to actually process the switching signal from input to output.

The main disadvantage of the Gm-C stage is that it cannot drive a low-impedance. Since any resistive loading will steal charge from the load capacitor, only capacitive stages may be driven by the Gm-C stage. Consequently, once one has chosen a Gm-C first stage, all proceeding stages must then be Gm-C—unless one places a voltage buffer in-between the Gm-C and an active-RC.

In the case of the Gm-C, the weighed sum of the integrator outputs must be handled by a separate stage. Essentially, each of the k1, k2, k3 gains would be a separate transconductor that can get wire-summed (summing current) to produce the output z. However, with the active-RC, separate summing stages are not required. By adding a resistor feedback to the active-RC stages, we can allow each stage to pass through a linear term, thus creating a weighted sum of the integrator outputs:

For your clarity and my sanity, I have excluded the resonant γ term. The overall transfer function is

(1/(sC2R1))×(R3/R2 + 1/(sC3R2))×(R5/R4 + 1/(sC5R4))

Which is of the original form

(K₁s² + K₂s + K₃)/s³

Ideally, one would like the best of both worlds: the ability for the DAC current to bypass the op-amp as in the Gm-C, the voltage-mode output of the active-RC, and the direct weighted sum of the active-RC. It turns out that one can do so by developing a floating DAC that directly sums on the capacitor C1 in the active-RC. To do so, one actually builds two complementary DAC’s that in unison drive each side of the capacitors C1:

Of course, these DAC’s will not exactly match each other. However, the beauty of this configuration is that when the DAC’s do mismatch, the op-amp can source/sink the current. Nonetheless, if the DAC’s match to 40 dB, we have reduced the high-frequency current demands on the op-amp by 40 dB and increased the linearity by 40 dB.

I had initially thought that this DAC summation method was a novel idea. I don’t have a reference for it, but I am informed that it falls into the class of ideas that are so old they are new.

In the future, I will post another trick one can do to the noise-shaping filter (in combination with what I’ve shown here) that linearizes the continuous-time sigma-delta. Consider subscribing via RSS or email.

Related posts:

1. Example Simulink model & scripts for continuous-time sigma-delta ADC I've put together a 2nd order continuous sigma-delta Simulink model...
2. Unity STF | A sigma-delta linearization method In a previous post, I discussed the trade-offs in linearity...
3. A simple sigma-delta loop In my post on Quantization, I noted that quantization noise...

Executive Summary

For time-invariant blocks, such as:

• LNA’s
• RF Amplifiers
• Baseband filters
• Operation Amplifiers
• Linear regulators

Use dc analysis to determine bias points, ac analysis to determine gain, noise analysis to measure noise.
Use hb analysis to determine two-tone linearity (IM2, IM3). Use (in order of preference) hb, pss, or transient to determine single-tone linearity (HD2/3/4/5).

In some cases, elevated noise can occur with large inputs. Use (in order of preference) hbnoise or pnoise to measure that.
For blocks with feedback, such as:

• Linear regulators
• Active filters

Use stb analysis to simulate loop gain and determine phase margin.

For time-varying blocks, such as:

• Mixers
• Switched-capacitor circuits

Use dc analysis to determine bias points, use steady analysis to simulate LO operation, and pac + pnoise to simulate small-signal ac and noise inputs/outputs.
Use hb analysis for single input tone linearity (LO + single input tone) and multi-tone simulation (LO + two or more inputs). Use hbnoise to simulate elevated noise levels due to large inputs (blockers).

You can get an estimate of the dynamic operation from looking at ac analysis with switch set in a desired state. For example, with a switched-mode mixer, I might put a dc source on the LO and look at the gain through the Mixer (from LNA to PMA). I can also do a noise simulation to get an estimate of where the noise is coming from. However, these simulations don’t include the actual mixing effects.

Taxonomy of systems

Before we delve into what analysis is best for what problem, we should first consider the classification of systems in general. They can basically be broken down by the following criteria:

• time base: discrete-time (DT) or continuous-time (CT)
• response dependence: time-variant (TV) or time-invariant (TI)
• linearity: linear or nonlinear

You probably will encounter systems that as a whole do not fit into each of these categories. However, each system can be broken down into a component (call it a sub-system) that fits in each of the above categories. For example, a sigma-delta DAC generally has a discrete-time modulator and a continous-time reconstruction filter. For brevity, we will simply use the term system rather than sub-system.

The first two categories are basically black-and-white: a system is either discrete-time or continuous-time. Likewise, a system is either time-variant or time-invariant. Linearity, however, is a relative term. All circuits are nonlinear. However, if their nonlinearities (distortion) is low enough, we call them linear.

A circuit is discrete-time if it is triggered by some clock (i.e. it approximates some difference equation). Examples of discrete-time circuits are switched-capacitor filters, most sigma-delta modulators, and all digital logic. A circuit is continous-time if it operates continously without being triggered by a clock (i.e. it approximates some differential equation). Examples of continuous-time circuits are filters, linear regulators, and all RF circuits (excluding TI’s Digital Radio Processing).

A circuit is time-invariant if its input-output relationship does not change with time. For example, if I send an input x and get an output y, do I get the same output if delay x by (say) 1 μs? If not, the circuit is time-variant. If so (and if the same holds true for not just a 1 μs delay, but all delays), the circuit is time-invariant. Most circuits you encounter are time-invariant, such as filters, amplifiers, almost all RF circuits. Examples of time-variant circuits are RF mixers (analog multipliers) such as the Gilbert cell and the MOS chopping mixer. I’ve heard many say that it’s wierd that we want mixers to be linear, when a mixer itself is a non-linear device. In truth, the ideal mixer is linear. However, in the past, the preferred way of creating a mixer was to sum two signals (an RF input and an LO) and pass them through a non-linear device (a diode for example); the resulting cross-multiplication (through the nonlinearity of the device) would cause a mixing. The ideal mixer, however, is both linear and time-variant (with respect to its RF input/output and baseband output/input, not its LO).

A circuit is linear if it obeys the rule that the input α×u₁ + β×u₂ (composed by a weighted sum of any signals u₁ and u₂) yields an output α×y₁ + β×y₂. That is, the output is proportional to the input, including sums of different inputs. If I double the input, I should get double the output. I should also be able to sum two different inputs and have the sum of two different outputs come out.

Circuit analyses

op

An operating point analysis solves KCL in a static condition–that is all derivatives are zero, and nothing is varying with respect to time. This analysis is useful for determining bias conditions. It is also used as a starting point for ac analysis and for noise analysis. In Spectre, an op analysis is a special case of a dc analysis (you select the “save operating point information” during a dc analysis).

This analysis is useful for all circuits. Initial conditions or nodese