Foster’s reactance theorem states that any reactance increases as a function of frequency . This is true of the impedance looking into an antenna, where the reactance may be a large part of the overall impedance. The task in matching the antenna (for maximum power transfer and therefore maximum SNR) is to cancel the reactance (or susceptance) and match the resistance.
Unfortunately, this can’t be done over a large range, because as Foster’s reactance theorem states, as soon as you deviate a little from your center frequency, both the inductive reactance of your antenna and the reactance of whatever you’re using to cancel it (most likely a capacitive element) both increase (go toward ). So, for every change in frequency from the center frequency, your antenna reactance goes up by some amount , but your matching element’s reactance also goes up by some amount .
If you had a Non-Foster element, the reactance of your tuning element would go down by some amount , compensating for the increased reactance of the antenna. You would then have a broadband (or broader) match.
Most attempts to do this have required the use of active elements (such as gyrators) so synthesis a negative impedance. However, I’m wondering if a switched-capacitor circuit can be used to synthesize this Non-Foster reactance. Most analyses of switched-capacitor circuits show that they are synthetic resistors at frequencies far below the switching frequency. However, what does the impedance look like near the switching frequency? Read More »
You’ll notice that this post has Matt Miller listed as the author. Poojan requested Matt’s comments on his differential circuit post. Poojan was impressed with my comments enough that he decided to make it a follow-up post. So, this post is co-written by both Poojan and Matt.
I’ve been lucky enough to find myself in a team that’s intent on finding the best circuit design for a given application. This doesn’t happen often to many people, but I feel that I’ve had more than my share of this opportunity.
The conclusion is usually that we come up with some topology (let’s call it circuit X) that optimizes all the performance criteria. I walk away wanting to generalize the experience with the lesson that circuit X is the best circuit ever, and I want to use it everywhere.
Inevitably, I find that some other topology Y is better suited for some other application. There were some specific constraints or conditions on circuit X that don’t apply to circuit Y, and as a result, circuit Y is more optimal for application Y.
It is for this reason that I won’t say that differential circuits are always better than their single ended counter-part. I will say that in my experience, I’ve come across the case where the differential circuit–or, really, the differential approach–is more effective than its single-ended counterpart. However, that’s not why I’ve decided to write this post.
Unfortunately, I’ve come across several engineers that make the generalization error in the opposite direction: they state that single-ended circuits save current. I will present a counter-example that is sufficient to disprove this generalization. Keep in mind that it doesn’t prove the opposite generalization (that differential circuits are always better).
I generally don’t accept solicitations to post resumes, but I am making an exception for a very talented friend of mine.
I know a very good IC designer and PCB designer. My experience with him is as an IC layout designer. However, most of his PCB customers cite him as the best PCB layout designer they’ve come across. I’ll focus on his IC skills, since I can attest to that.
He’s most often hired as a consultant embedded in a design team. However, he’s capable of and set up for turn-key work (taking schematics and sending back GDS II). He’s skilled in Cadence (Virtuoso XL, Assura) and Mentor (IC Layout, Calibre) design tools.
He’s worked on the following products (since I’ve met him) and much more:
CMOS 90 nm transceiver IC including ADC/DAC, RF: massive integration effort, requiring careful shielding and differential matching of many RF/analog lines
IBM 8WL BiCMOS IC including high-linearity mixer with feedback: extremely compact layout, minimizing RF parasitics
CMOS 90 nm continuous-time sigma-delta ADC: detailed matching (common centroiding) of CMOS devices and matching of routing parasitics
TSMC 0.18 um CMOS class-D audio amplifier IC: integration and isolation of several analog blocks with large digital circuit
CMOS 0.18 um all-digital RF transmitter (resulted in this publication)
Each of the above has been a first-pass success. He contracted for over a decade at Motorola Labs (Motorola’s corporate research center at their headquarters near Chicago), Atmel, Freescale Semiconductor, and several Motorola product groups. He ran a circuit board development group at Tellabs. He’s extremely pleasant to work with and does very well in a team environment (both as a lead developer and as a team member).
I’ve been fielding quite a few questions lately about polar modulation. Indeed, polar modulators are theoretically more efficient. However, this does not need to be the case. I will highlight (technically, self-promote) a Cartesian scheme that can produce an RF signal as efficiently as a polar modulator—with fewer implementation issues. Read More »