Tag Archives: ADC

Dual DAC CTSD | Wider Bandwidth and Higher SNR — Part 2

Introduction So, we want to break down our continuous-time sigma-delta feedback into two paths: A low-precision tight loop that delivers the first sample to the quantizer A higher-precision loop that goes through a clock delay to minimize “metastability” (indecision)

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Continuous time sigma-delta ADC noise shaping filter circuit architectures

The continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) is a class of sigma-delta analog-to-digital converters that utilize a continuous-time noise-shaping filter (NSF | H(s)). In this post, I analyze a few noise-shaping filter (NSF) architectures that affect highly linear CTSD ADC’s.

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Calculation of ADC SNR in Cadence Skill/Ocean

However, here’s how I compute SNR/SNDR from an FFT using Cadence Ocean/Skill.

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Example Simulink model & scripts for continuous-time sigma-delta ADC

I’ve put together a 2nd order continuous sigma-delta Simulink model as a starting point. This is the multi-port feedback configuration (feeds back into input of 1st and 2nd integrators).

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Response to edaboard question “How can I deal with 3rd HD in a 2nd SigmaDelta Modulator”

In response to: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator It’s possible that the OTA is limiting you. Doing a matlab model of the sigma-delta and running it should tell you whether it is a circuit problem or a system-level problem. My hunch is that it’s a system-level problem: the […]

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