Tag Archives: CMOS

You want latches? We got latches | Flip-Flop Design

By Poojan Wagh | Published: December 14, 2008
The two inverters chasing their tail to the right of the input inverters represent a memory unit (i.e. a latch). When one output is high the other one is forced low. This low output then reinforces the first output being high. These two inverters form a positive feedback system.
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MOS Diffusion Parasitics

By Poojan Wagh | Published: December 9, 2008
I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance.
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Supply voltage, current, RF impedance, and CMOS scaling

By Poojan Wagh | Published: November 11, 2008
Consider the circuit below: Let’s say that you’ve designed the circuit with a supply voltage (VDD) of 2.4 V. It’s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are: PMOS: IDP×VDSATP = 10 mA×0.6 [...]
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A compact common-mode feedback loop | using a PMOS triode device for CMFB

By Poojan Wagh | Published: October 24, 2008
One of the defining traits of analog CMOS designers is the ability to implement a common-mode feedback (CMFB) loop. When the input devices on a differential pair are all NMOS (or NPN), and the loads are either inductors or resistors, a common-mode feedback loop is unnecessary, because the output resistance of the differential pair is [...]
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