I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance.
Tag Archives: diffusion
MOS Diffusion Parasitics
Posted in Analog Professional Also tagged CMOS, fully custom, high speed logic, layout, parasitics 1 Comment