Tag Archives: feedback

Dual DAC CTSD | Wider Bandwidth and Higher SNR — Part 2

By Poojan Wagh | Published: March 10, 2009
Introduction So, we want to break down our continuous-time sigma-delta feedback into two paths: A low-precision tight loop that delivers the first sample to the quantizer A higher-precision loop that goes through a clock delay to minimize “metastability” (indecision)
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A compact common-mode feedback loop | using a PMOS triode device for CMFB

By Poojan Wagh | Published: October 24, 2008
One of the defining traits of analog CMOS designers is the ability to implement a common-mode feedback (CMFB) loop. When the input devices on a differential pair are all NMOS (or NPN), and the loads are either inductors or resistors, a common-mode feedback loop is unnecessary, because the output resistance of the differential pair is [...]
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Example Simulink model & scripts for continuous-time sigma-delta ADC

By Poojan Wagh | Published: September 2, 2008
I've put together a 2nd order continuous sigma-delta Simulink model as a starting point. This is the multi-port feedback configuration (feeds back into input of 1st and 2nd integrators).
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