Tag Archives: load

Fundamentals of Analog/RF design: Noise, Signal, Power

Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog/RF design: that to maintain a given SNR, a certain amount of power must be consumed […]

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A compact common-mode feedback loop | using a PMOS triode device for CMFB

One of the defining traits of analog CMOS designers is the ability to implement a common-mode feedback (CMFB) loop. When the input devices on a differential pair are all NMOS (or NPN), and the loads are either inductors or resistors, a common-mode feedback loop is unnecessary, because the output resistance of the differential pair is […]

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