Tag Archives: sigma delta

Dual DAC CTSD | Wider Bandwidth and Higher SNR — Part 2

Introduction So, we want to break down our continuous-time sigma-delta feedback into two paths: A low-precision tight loop that delivers the first sample to the quantizer A higher-precision loop that goes through a clock delay to minimize “metastability” (indecision)

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Impulse Invariant Transform

Introduction The impulse invariant transform (IIT) is a method of taking a continuous-time system H(s) and converting it to a discrete-time system. There are multiple ways of doing this, but the IIT does so with the constraint that the impulse response of the discrete-time system is a sampled version of the impulse response of the […]

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The Viterbi Sigma-Delta (at CircuitSage)

I’ve posted a guest article at Circuit Sage, detailing the derivation of a “Viterbi” over-sampling data converter. I’m quite proud of this one. Go over and check it out.movie Mechanic: Resurrection 2016 streaming FYI: this is also the reason I didn’t post directly to this site this week. I try to do a post per […]

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Unity STF | A sigma-delta linearization method

In a previous post, I discussed the trade-offs in linearity of several continuous-time sigma-delta schemes. In this post, I will describe a method that linearizes the sigma-delta noise-shaping filter (NSF). That is, the scheme presented in this article greatly suppresses the linearity requirements on the noise-shaping filter. This method applies to both discrete-time and continuous-time […]

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Continuous time sigma-delta ADC noise shaping filter circuit architectures

The continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) is a class of sigma-delta analog-to-digital converters that utilize a continuous-time noise-shaping filter (NSF | H(s)). In this post, I analyze a few noise-shaping filter (NSF) architectures that affect highly linear CTSD ADC’s.

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Example Simulink model & scripts for continuous-time sigma-delta ADC

I’ve put together a 2nd order continuous sigma-delta Simulink model as a starting point. This is the multi-port feedback configuration (feeds back into input of 1st and 2nd integrators).

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Response to edaboard question “How can I deal with 3rd HD in a 2nd SigmaDelta Modulator”

In response to: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator It’s possible that the OTA is limiting you. Doing a matlab model of the sigma-delta and running it should tell you whether it is a circuit problem or a system-level problem. My hunch is that it’s a system-level problem: the […]

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