Tag Archives: SNR power

Supply voltage, current, RF impedance, and CMOS scaling

By Poojan Wagh | Published: November 11, 2008
Consider the circuit below: Let’s say that you’ve designed the circuit with a supply voltage (VDD) of 2.4 V. It’s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are: PMOS: IDP×VDSATP = 10 mA×0.6 [...]
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Fundamentals of Analog/RF design: Noise, Signal, Power

By Poojan Wagh | Published: November 5, 2008
Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog/RF design: that to maintain a given SNR, a certain amount of power must be consumed [...]
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