{"id":325,"date":"2008-11-05T00:32:23","date_gmt":"2008-11-05T05:32:23","guid":{"rendered":"https:\/\/www.circuitdesign.info\/blog\/2008\/11\/fundamentals-of-analogrf-design-noise-signal-power\/"},"modified":"2008-11-24T22:36:00","modified_gmt":"2008-11-25T03:36:00","slug":"fundamentals-of-analogrf-design-noise-signal-power","status":"publish","type":"post","link":"https:\/\/www.circuitdesign.info\/blog\/2008\/11\/fundamentals-of-analogrf-design-noise-signal-power\/","title":{"rendered":"Fundamentals of Analog\/RF design: Noise, Signal, Power"},"content":{"rendered":"

Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog\/RF design: that to maintain a given SNR, a certain amount of power must<\/strong> be consumed by an analog\/RF circuit.<\/p>\n

<\/p>\n

Transconductors<\/h2>\n

MOS Thermal Noise<\/h3>\n

Shown below is a disembodied MOS transconductor:<\/p>\n

\"scan0085a\"<\/a><\/p>\n

It takes an input voltage vi and outputs a current io<\/sub>. To avoid clipping, io<\/sub> would need to be less than ID<\/sub>, the bias voltage on the MOS transistor. However, let\u2019s say that for some linearity requirement (IM2<\/sub>, IM3<\/sub>, IM5<\/sub>, etc.) that we limit io<\/sub> to be less than \u03b1\u00d7ID<\/sub>.<\/p>\n

So, we know the signal power is:<\/p>\n

Psig<\/sub> = (\u03b1\u00d7ID<\/sub>)2<\/sup> = \u03b1^2\u00d7ID<\/sub>^2<\/p>\n

This power is computed as a current; we could equally have the transconductor drive a specified load impedance and compute all the quantities as voltage, but they will not change the end result.<\/p>\n

Likewise, the noise current power is:<\/p>\n

Pnoise = 8\u00d7k\u00d7T\u00d7gm<\/sub>\u00d7B\/3<\/p>\n

At this point, it is useful to represent gm<\/sub> in terms of voltage and current:<\/p>\n

gm<\/sub> = 2\u00d7ID<\/sub>\/VDSat<\/sub>
\n\u2192 Pnoise<\/sub> = 16\u00d7k\u00d7T\u00d7ID<\/sub>\u00d7B\/(3\u00d7VDSat<\/sub>)\n<\/p>\n

Therefore:<\/p>\n

SNR = Psig<\/sub>\/Pnoise<\/sub> = 3\u00d7\u03b1^2\u00d7ID<\/sub>\u00d7VDSat<\/sub>\/(16\u00d7k\u00d7T\u00d7B)<\/p>\n

Note that the term ID<\/sub>\u00d7VDSat<\/sub> is a lower-bound on the power dissipated across the FET. In fact, the actual power dissipated across the FET is ID<\/sub>\u00d7VDS<\/sub>, which is actually greater than ID<\/sub>\u00d7VDSat<\/sub>, since VDS<\/sub> > VDS<\/sub> to keep the FET in saturation.<\/p>\n

To summarize:<\/p>\n

    \n
  1. For a given SNR, we need a certain ID<\/sub>\u00d7VDSat<\/sub> product (Pmin)<\/sub><\/li>\n
  2. The actual power dissipated by the FET is greater than this ID<\/sub>\u00d7VDSat<\/sub> product Pmin<\/sub><\/li>\n
  3. Therefore, the SNR dictates how much power we must dissipate<\/li>\n<\/ol>\n

    BJT Noise<\/h3>\n

    A similar argument holds for the BJT.\u00a0 The difference is that the BJT\u2019s are less sensitive to voltage, since due to their exponential current-voltage curve, the voltage varies very little:<\/p>\n

    \"scan0083a\"<\/a><\/p>\n

    Pnoise<\/sub> = 2\u00d7k\u00d7T\u00d7B\u00d7IC<\/sub>\/Vt<\/sub><\/p>\n

    Psig<\/sub> = \u03b1^2\u00d7IC<\/sub>^2<\/p>\n

    SNR = \u03b1^2\u00d7IC<\/sub>\u00d7Vt<\/sub>\/(2\u00d7k\u00d7T\u00d7B)<\/p>\n

    Once again, this IC<\/sub>\u00d7Vt<\/sub> is a lower-bound on the noise dissipated across the BJT: VBE<\/sub> > Vt<\/sub> and VCE<\/sub> > VBE<\/sub> \u2192 VCE<\/sub> > Vt<\/sub>. The true power dissipated across the BJT is IC<\/sub>\u00d7VCE<\/sub> which is greater than Pmin = IC<\/sub>\u00d7Vt<\/sub>, and to maintain a certain SNR, we have Pmin<\/sub> = SNR\u00d7k\u00d7T\u00d7B\/(\u03b1^2).<\/p>\n

    Loads<\/h2>\n

    Resistor Noise<\/h3>\n

    We now veer off into load country, considering resistor loads for our transconductor:<\/p>\n

    \"scan0084a\"<\/a><\/p>\n

    Considering only noise due to the resistor, and making the assumption that the signal current is once again limited to \u03b1\u00d7ID<\/sub> (where ID<\/sub> = IR<\/sub>):<\/p>\n

    Pnoise<\/sub> = 4\u00d7k\u00d7T\u00d7B\/R = 4\u00d7k\u00d7T\u00d7B\u00d7IR<\/sub>\/VR<\/sub><\/p>\n

    SNR = \u03b1^2\u00d7IR<\/sub>\u00d7VR<\/sub>\/(4\u00d7k&Times;T\u00d7B)<\/p>\n

    Note that this case is not general: in many cases, we don’t have to have IR<\/sub> = ID<\/sub>, so the Psig<\/sub> has nothing to do with the resistor current. My intent is not to generalize to that much degree. I assume we have a transconductor–and every transconductor has to have a load (resistive, inductive, or active) that supplies dc current.<\/p>\n

    Active Loads<\/h3>\n

    Going through the math, one finds that active loads (BJT or MOS) also follow a similar derivation: the noise contributed by the load is proportional to the current to minimum-voltage ratio of the load. Also, the signal current coming into the load is constrained by the load current, since that same load current flows through the transconductor:<\/p>\n

    MOS Load: Pnoise<\/sub> = 16\u00d7k\u00d7T\u00d7ID<\/sub>\u00d7B\/(3\u00d7VDSat<\/sub>) | Psig<\/sub> = \u03b1^2\u00d7ID<\/sub><\/p>\n

    BJT Load: Pnoise<\/sub> = 2\u00d7k\u00d7T\u00d7B\u00d7IC<\/sub>\/Vt<\/sub> | Psig<\/sub> = \u03b1^2\u00d7IC<\/sub><\/p>\n

    Final Note<\/h2>\n

    One final note: many times circuit designers think that they need to maximize gm<\/sub> of devices to minimize noise. This optimum is not always the case. Generally, for a transconductor, better gm yields better SNR (assuming linearity is not an issue). However, the gm<\/sub> of a load makes it add more (current) noise without improving signal power. Therefore, for loads, one wants to minimize<\/em> gm<\/sub>.<\/p>\n","protected":false},"excerpt":{"rendered":"

    Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog\/RF design: that to maintain a given SNR, a certain amount of power must be consumed […]<\/p>\n","protected":false},"author":4,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[3],"tags":[6,77,76,61,85,30,9,59,106],"class_list":["post-325","post","type-post","status-publish","format-standard","hentry","category-analog-pro","tag-analog","tag-gain","tag-load","tag-noise","tag-power","tag-rf","tag-signal","tag-snr","tag-snr-power"],"jetpack_featured_media_url":"","jetpack_shortlink":"https:\/\/wp.me\/poCEy-5f","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/325","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/comments?post=325"}],"version-history":[{"count":11,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/325\/revisions"}],"predecessor-version":[{"id":331,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/325\/revisions\/331"}],"wp:attachment":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/media?parent=325"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/categories?post=325"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/tags?post=325"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}