![\"scan0088\"](\"https:\/\/www.circuitdesign.info\/blog\/wp-content\/uploads\/2008\/11\/scan0088.jpg\")
<\/a><\/p>\nLet\u2019s say that you\u2019ve designed the circuit with a supply voltage (VDD)<\/sub> of 2.4 V. It\u2019s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR<\/a> are:<\/p>\n PMOS: IDP<\/sub>\u00d7VDSATP<\/sub> = 10 mA\u00d70.6 V The differential input impedance is 2\/gm<\/sub> of the NMOS transistors:<\/p>\n Rin = 2\/gmn<\/sub> = VDSATN<\/sub> \/ IDN<\/sub> = 1.2 V \/ 10 mA = 120 \u03a9 You need a balun anyway, so you have a transformer that steps up from 50 \u03a9 to 120 \u03a9<\/p>\n Great. The product ships and it sells well.<\/p>\n Your boss\/customer comes by and asks you for a next generation part. They want to simplify the power regulation scheme on their products, so they absolutely have to have a 1.2 V supply. There\u2019s no negotiation on this supply voltage.<\/p>\n <\/p>\n So, you start deciding on how to scale this design to maintain SNR. You may want to move to a different process node, but I\u2019ll exclude the effects of doing so; you\u2019ll find that they won\u2019t change the result.<\/span> You decide that since your supply voltage has gone down by 1\/2, you should scale all VDSAT\u2019s by 1\/2. You realize, though, that in order to maintain SNR, you then need to double the current:<\/p>\n PMOS: IDP<\/sub>\u00d7VDSATP<\/sub> = 20 mA\u00d70.3 V Essentially, you are maintaining power by doubling current and halving voltage. That’s okay for your customer: he\/she just wants a lower supply, not less power. The input impedance is now 30 \u03a9<\/strong> because Rin<\/sub> = VDSATN<\/sub> \/ IDN<\/sub> = 0.6 V \/ 20 mA, but more fundamentally, the circuit expects half the input voltage and twice the input current.<\/p>\n You now need a transformer that steps down<\/strong> from 50 \u03a9 to 30 \u03a9.<\/p>\n I haven’t seen this relationship between supply voltage and RF input impedance published anywhere else. Post a comment I’ve missed it.<\/span> I have only shown it for the common-gate amplifier. However, it is my hunch (just based on the fundamentals) that the same conclusion will be reached for other RF circuits (inductor-degenerated LNA, Gilbert cells, etc).<\/p>\n The relationship leads me to believe that as CMOS scales to lower and lower voltages, RF designers will start designing for lower and lower impedance. Alternatively, RF designers may find the optimum supply voltage for a 50-\u03a9 input impedance and stick with it. That’s possibly why many RF transceivers are at 2.4 V. The curious thing about that voltage is that most RF front-ends I’ve come across operating at 2.4 V have a step-up transformer to 200 \u03a9.<\/p>\n If you like this post, consider subscribing (via RSS feed-reader<\/a> or by email<\/a>).<\/p>\n","protected":false},"excerpt":{"rendered":" Consider the circuit below: Let\u2019s say that you\u2019ve designed the circuit with a supply voltage (VDD) of 2.4 V. It\u2019s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are: PMOS: IDP\u00d7VDSATP = […]<\/p>\n","protected":false},"author":4,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[3],"tags":[75,88,85,30,89,59,106,87,90],"class_list":["post-338","post","type-post","status-publish","format-standard","hentry","category-analog-pro","tag-cmos","tag-impedance","tag-power","tag-rf","tag-scaling","tag-snr","tag-snr-power","tag-supply","tag-voltage"],"jetpack_featured_media_url":"","jetpack_shortlink":"https:\/\/wp.me\/poCEy-5s","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/338","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/comments?post=338"}],"version-history":[{"count":5,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/338\/revisions"}],"predecessor-version":[{"id":423,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/338\/revisions\/423"}],"wp:attachment":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/media?parent=338"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/categories?post=338"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/tags?post=338"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\nNMOS: IDN<\/sub>\u00d7VDSATN<\/sub> = 10 mA\u00d71.2 V
\nYou have 0.6 V of headroom at the output for signal swing.<\/p>\n
\nwhere we have the used the relation gm<\/sub> = 2\u00d7ID<\/sub>\/VDSAT<\/sub> which excludes short-channel effects. Including short-channel effects changes the relationship, but won’t change the conclusion of this topic.<\/span><\/p>\n
\nNMOS: IDN<\/sub>\u00d7VDSATN<\/sub> = 20 mA\u00d70.6 V
\nYou have 0.3 V of headroom at the output for signal swing.<\/p>\n