![\"scan0098a\"](\"https:\/\/www.circuitdesign.info\/blog\/wp-content\/uploads\/2008\/11\/scan0098a1.jpg\")
<\/a><\/p>\nNote that H(s) is a continuous-time filter (s-domain) and there is a DAC in the feedback path to convert from digital back to analog. The comparator shown is a clocked comparator, producing a digital word Y (N-bit).<\/p>\n
This article will focus on the choice of architectures for H(s). I will assume the following 3rd-order topology for H(s): A series of integrators are cascaded and then summed (with weightings k1, k2, and k3) to produce the input z to the comparator.\u00a0 This filter implements\n<\/p>\n (K1<\/sub>s2<\/sup> + K2<\/sub>s + K3<\/sub>)\/s3<\/sup><\/p>\n Often times, a noise-transfer zero is desired (to widen the noise-shaped bandwidth); this can be accommodated with the following:<\/p>\n The feedback term \u03b3\/s creates a (resonant) pole in the noise-shaping filter which maps to an imaginary zero in the noise transfer function (NTF).<\/p>\n Typically, the active-RC configuration is used for continuous-time filters that are to be tightly controlled and where high linearity is necessary. The first integrator (for example) is composed of a stage shown below:<\/p>\n The analog input voltage is converted to a current. Likewise, the DAC feedback voltage is converted to a current. These currents are subtracted into the summing junction and integrated on the capacitor C.<\/p>\n Unfortunately, the main disadvantage of this topology is that the op-amp must now source and sink the DAC current pulse. The response of the op-amp creates an inter-symbol interference problem. The integrated current follows the pulse response of the op-amp. However, when three positive pulses are generated from the DAC, their integrated value does not equal the integrated value of a +1, \u20131, and +1 sequence of pulses:<\/p>\n In short, the op-amp has an easier time with the DAC maintains a constant output than when it transitions. As a result, the integrated value is signal-dependent, which means it is nonlinear. This effect is worse when the op-amp slews, but occurs even when the op-amp operates in a linear manner.<\/span><\/p>\n A popular alternative to the active-RC is the Gm-C architecture:<\/p>\n In this case, a (current-mode) DAC\u2019s output is directly summed with the signal current onto an integrated capacitor (which I thoughtfully forgot to draw in the illustration). This architecture isolates the DAC signal from the analog input signal. Consequently, the transconductor requirements are greatly relaxed; it only needs to tolerate the DAC switching on its output, but does not need to actually process the switching signal from input to output.<\/p>\n The main disadvantage of the Gm-C stage is that it cannot drive a low-impedance. Since any resistive loading will steal charge from the load capacitor, only capacitive stages may be driven by the Gm-C stage. Consequently, once one has chosen a Gm-C first stage, all proceeding stages must then be Gm-C\u2014unless one places a voltage buffer in-between the Gm-C and an active-RC.<\/p>\n In the case of the Gm-C, the weighed sum of the integrator outputs must be handled by a separate stage. Essentially, each of the k1, k2, k3 gains would be a separate transconductor that can get wire-summed (summing current) to produce the output z. However, with the active-RC, separate summing stages are not required. By adding a resistor feedback to the active-RC stages, we can allow each stage to pass through a linear term, thus creating a weighted sum of the integrator outputs:<\/p>\n For your clarity and my sanity, I have excluded the resonant \u03b3 term. The overall transfer function is<\/p>\n (1\/(sC2R1))\u00d7(R3\/R2 + 1\/(sC3R2))\u00d7(R5\/R4 + 1\/(sC5R4))<\/p>\n Which is of the original form<\/p>\n (K1<\/sub>s2<\/sup> + K2<\/sub>s + K3<\/sub>)\/s3<\/sup><\/p>\n Ideally, one would like the best of both worlds: the ability for the DAC current to bypass the op-amp as in the Gm-C, the voltage-mode output of the active-RC, and the direct weighted sum of the active-RC. It turns out that one can do so by developing a floating DAC that directly sums on the capacitor C1 in the active-RC. To do so, one actually builds two complementary DAC\u2019s that in unison drive each side of the capacitors C1:<\/p>\n Of course, these DAC\u2019s will not exactly match each other. However, the beauty of this configuration is that when the DAC\u2019s do mismatch, the op-amp can source\/sink the current. Nonetheless, if the DAC\u2019s match to 40 dB, we have reduced the high-frequency current demands on the op-amp by 40 dB and increased the linearity by 40 dB.<\/p>\n I had initially thought that this DAC summation method was a novel idea. I don\u2019t have a reference for it, but I am informed that it falls into the class of ideas that are so old they are new.<\/p>\n In the future, I will post another trick one can do to the noise-shaping filter (in combination with what I\u2019ve shown here) that linearizes the continuous-time sigma-delta. Consider subscribing via RSS<\/a> or email<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":" The continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) is a class of sigma-delta analog-to-digital converters that utilize a continuous-time noise-shaping filter (NSF | H(s)). In this post, I analyze a few noise-shaping filter (NSF) architectures that affect highly linear CTSD ADC\u2019s.<\/p>\n","protected":false},"author":4,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[3],"tags":[102,19,48,103,26,105,44],"class_list":["post-407","post","type-post","status-publish","format-standard","hentry","category-analog-pro","tag-active-rc","tag-adc","tag-continuous-time","tag-gm-c","tag-linearity","tag-noise-shaping-filter","tag-sigma-delta"],"jetpack_featured_media_url":"","jetpack_shortlink":"https:\/\/wp.me\/poCEy-6z","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/407","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/comments?post=407"}],"version-history":[{"count":7,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/407\/revisions"}],"predecessor-version":[{"id":418,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/407\/revisions\/418"}],"wp:attachment":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/media?parent=407"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/categories?post=407"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/tags?post=407"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a>A +1, -1, +1 sequence results in an integrated value of +0.6-0.6+0.6 = 0.6 …<\/p>\n<\/a>… whereas a +1, +1, +1 sequence results in an integrated value of +0.6+1.0+1.0 = 2.6<\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n