{"id":454,"date":"2008-11-29T15:14:46","date_gmt":"2008-11-29T20:14:46","guid":{"rendered":"https:\/\/www.circuitdesign.info\/blog\/2008\/11\/typical-cmos-deviceprocess-options\/"},"modified":"2008-12-02T23:34:43","modified_gmt":"2008-12-03T04:34:43","slug":"typical-cmos-deviceprocess-options","status":"publish","type":"post","link":"https:\/\/www.circuitdesign.info\/blog\/2008\/11\/typical-cmos-deviceprocess-options\/","title":{"rendered":"Typical CMOS device\/process options"},"content":{"rendered":"

I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let\u2019s go over some process options that effect leakage.<\/p>\n

Core Devices<\/h2>\n

Typically, foundries offer a few variations of there processes. I will call them general purpose (GP) and low power (LP). They differ in what I call the core devices, after which a process is usually named\u2014for example, CMOS090<\/em> (90 nm) or TSMC 0.18\u03bcm<\/em>.<\/p>\n

GP<\/h3>\n

The GP represents the state of the art and usually drives large digital IC\u2019s, including general purpose microprocessors and DSP\u2019s. The traits of the GP process are a lower threshold and supply voltage, and possibly smaller effective gate length.<\/p>\n

LP<\/h3>\n

The LP is usually a variant of the GP process optimized to reduce leakage (at the expense of speed). The LP option is usually used for highly integrated analog & RF CMOS IC\u2019s, such as radios (RF transceivers), ADC\u2019s, etc. Typically, the LP allows for a slightly higher supply voltage and sometimes has a slightly larger effective gate length. However, the main trait of the LP process is that the threshold is increased a bit from the GP process to allow for lower leakage. I\u2019m not entirely sure if the higher supply voltage and gate length are intentional or are a byproduct of the higher threshold.<\/span><\/p>\n

I\/O Devices<\/h2>\n

Almost universally, all modern processes offer an \u201cI\/O\u201d device. This is essentially a device from a prior process node (1.8 V, 2.5 V, or 3.3 V) with a larger gate length (0.18 um, 0.25 um, or 0.35 um). They are provided from a digital perspective as devices for pad drivers etc. However, they usually form the workhorse of analog\/RF IC\u2019s especially at baseband<\/span>.<\/p>\n

Device options<\/h2>\n

In both the GP and LP flavors, there are additional device options not necessarily universally, but usually<\/span>:<\/p>\n