{"id":50,"date":"2008-06-22T12:27:18","date_gmt":"2008-06-22T21:27:18","guid":{"rendered":"http:\/\/www.circuitdesign.info\/?p=50"},"modified":"2020-11-01T18:40:47","modified_gmt":"2020-11-02T00:40:47","slug":"quick-regulator-design-part-1-load-capacitance","status":"publish","type":"post","link":"https:\/\/www.circuitdesign.info\/blog\/2008\/06\/quick-regulator-design-part-1-load-capacitance\/","title":{"rendered":"Quick Regulator Design \u2014 Part 1: Load Capacitance"},"content":{"rendered":"\n

In this post, I will detail how I designed a regulator quickly. The idea here wasn’t to get the best performing regulator, but just one that did the job.<\/p>\n\n\n\n

I do care about performance, area, and power, just not as much in this case. The most important thing was to meet the schedule. If I didn’t have a regulator, I would have no ADC to measure. So, any<\/em> regulator was better than no regulator.<\/p>\n\n\n\n

After I was done, I realized that the result was a really good basic regulator\u00e2\u20ac\u201done that someone could design quickly, and then build upon to realize something more optimal.<\/p>\n\n\n\n\n\n\n\n

The regulator was meant to power the comparator in a sigma-delta ADC. This comparator (the load circuit) is comprised of both analog (constant-current) and switching circuits. The analog section impinges very little on its supply. We therefore focus on the switching portions of the load circuit.<\/p>\n\n\n\n

Switching Circuit Load<\/h2>\n\n\n\n

Before we consider the design of the regulator, let’s consider how a switching circuit draws power from its supply.<\/p>\n\n\n\n

Take the switching diagram of an inverter with a capacitor load $C_L$, shown below:<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

This circuit dissipates current from the supply in two steps. In the first phase ($\\phi_0$), the upper switch connects the load to supply. A charge of QL<\/sub>=CL<\/sub>*VDD<\/sub> has been sourced from supply. During the second phase ($\\phi_1$), this charge is taken off the load capacitor and dissipated to ground.<\/p>\n\n\n\n

Regulator with Switching Load<\/h2>\n\n\n\n

Let’s for now model the regulator as a fixed resistor between supply (VS<\/sub>) and its output (VR<\/sub>). Note that VR<\/sub> is also the supply to the switching circuit.<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

This model is valid for cases when the feedback loop of the regulator isn’t fast enough to correct the output voltage. This short\/quick transient is exactly what we’ll consider here.<\/p>\n\n\n\n

During the phase ($\\phi_0$) when the inverter pulls charge from supply, there’s essentially an RC formed between the supply VS<\/sub>, the resistance of the regulator, RR<\/sub>, and the load capacitor CL<\/sub>. The regulated voltage takes a dip down and settles back:<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

This is obviously a bad situation: the regulated output takes a large droop. In the case of my comparator, this would definitely effect the linearity, since the droop in supply would be signal-dependent.<\/p>\n\n\n\n

Here’s the dirty little secret: for RF circuits and high-speed circuits, the regulator is too slow to do anything about these switching transients<\/strong>. The regulator feedback can do nothing to correct this droop.<\/p>\n\n\n\n

The Regulator Bypass Capacitor<\/h2>\n\n\n\n

To alleviate this droop problem, we put a capacitor on the regulator\u00e2\u20ac™s output:<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

Instead of sourcing charge through the regulator resistance, the charge can come off the bypass capacitor CR<\/sub>.<\/p>\n\n\n\n

Now, we have a switched-capacitor circuit. The load capacitor of the regulator is now connected to CR<\/sub>. Take, for example, the case where CR<\/sub> is 10x CL<\/sub>, the regulated output is 1.0 V, and the inverter starts out with a low (0 V) output:<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

When the inverter output now goes high, we have charge sharing between the load capacitor CL<\/sub> and the bypass capacitor CR<\/sub>:<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

Since the load capacitance is 10% of the bypass capacitance, 10% of the charge is transferred from the bypass capacitor to the load capacitor, and we get a 10% drop in the regulated output.<\/p>\n\n\n\n

More generally, if we design CR<\/sub> to be $F \\times C_L$, we will generally see a $\\frac{1}{F+1}$ droop in our regulated supply VR<\/sub>.<\/p>\n\n\n\n

An Effective CL<\/sub><\/h2>\n\n\n\n

Obviously, our circuit does not consist of a single inverter. So, how do we estimate CL<\/sub>? The method I use is to vary the switching frequency. If there is a clock that determines the frequency of $\\phi_0$ and $\\phi_1$, we can use that to determine the effective CL<\/sub> by varying the clock frequency. Recall that during every clock period, we above circuit dissipates a charge QL<\/sub> = CL<\/sub>*VR<\/sub> from VR<\/sub>.<\/p>\n\n\n\n

So, we have a relationship of current with switching frequency:<\/p>\n\n\n\n

$$I_R = I_{R0} + C_L \\times V_R \\times F_S$$<\/p>\n\n\n\n

$I_{R0}$ represents the current drawn by analog (constant-current biased & simple resistor) elements within the load circuit. We can back-solve for an effect $C_L$ by looking at the change in $I_R$ from a (say 10%) change in $F_S$:<\/p>\n\n\n\n

$$\\Delta I_R = C_L \\times V_R \\times \\Delta F_S$$<\/p>\n\n\n\n

$$ C_L = \\frac{\\Delta I_R}{V_R * \\Delta F_S} $$<\/p>\n\n\n\n

So, let’s for example consider the following table extracted from simulations:<\/p>\n\n\n\n

FS<\/sub><\/strong><\/td>IR<\/sub><\/strong><\/td><\/tr>
100 MHz<\/td>5 mA<\/td><\/tr>
110 MHz<\/td>5.1 mA<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

$$ C_L = \\frac{0.1 \\text{mA}}{1.0 \\text{V} * 10 \\text{MHz}} = 10 \\text{pF} $$<\/p>\n\n\n\n

I wanted to make sure that my regulator supply (VR<\/sub>) was rock solid. So, I chose CR<\/sub> to be 100 X 10 pF = 1 nF. (Like I said, I didn’t care that much about area in this case.)<\/p>\n","protected":false},"excerpt":{"rendered":"

In this post, I will detail how I designed a regulator quickly. The idea here wasn’t to get the best performing regulator, but just one that did the job. I do care about performance, area, and power, just not as much in this case. The most important thing was to meet the schedule. If I […]<\/p>\n","protected":false},"author":4,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[3],"tags":[],"class_list":["post-50","post","type-post","status-publish","format-standard","hentry","category-analog-pro"],"jetpack_featured_media_url":"","jetpack_shortlink":"https:\/\/wp.me\/poCEy-O","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/50","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/comments?post=50"}],"version-history":[{"count":13,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/50\/revisions"}],"predecessor-version":[{"id":1185,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/50\/revisions\/1185"}],"wp:attachment":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/media?parent=50"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/categories?post=50"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/tags?post=50"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}