{"id":753,"date":"2009-06-11T20:40:57","date_gmt":"2009-06-12T01:40:57","guid":{"rendered":"https:\/\/www.circuitdesign.info\/blog\/?p=753"},"modified":"2020-11-01T11:03:39","modified_gmt":"2020-11-01T17:03:39","slug":"the-benefits-of-differential-circuits","status":"publish","type":"post","link":"https:\/\/www.circuitdesign.info\/blog\/2009\/06\/the-benefits-of-differential-circuits\/","title":{"rendered":"The benefits of differential circuits"},"content":{"rendered":"\n

Introduction<\/h2>\n\n\n\n

From my personal blog<\/a>:<\/p>\n\n\n\n

I\u2019ve been lucky enough to find myself in a team that\u2019s intent on finding the best<\/em> circuit design for a given application. This doesn\u2019t happen often to many people, but I feel that I\u2019ve had more than my share of this opportunity.<\/p>\n\n\n\n

The conclusion is usually that we come up with some topology (let\u2019s call it circuit X<\/em>) that optimizes all the performance criteria. I walk away wanting to generalize the experience with the lesson that circuit X<\/em> is the best circuit ever, and I want to use it everywhere.<\/p>\n\n\n\n

Inevitably, I find that some other topology Y<\/em> is better suited for some other application. There were some specific constraints or conditions on circuit X<\/em> that don\u2019t apply to circuit Y<\/em>, and as a result, circuit Y<\/em> is more optimal for application Y<\/em>.<\/p>\n\n\n\n

It is for this reason that I won\u2019t say that differential circuits are always better than their single ended counter-part. I will say that in my experience, I\u2019ve come across the case where the differential circuit\u2013or, really, the differential approach<\/em>\u2013is more effective than its single-ended counterpart. However, that\u2019s not why I\u2019ve decided to write this post.<\/p>\n\n\n\n

Unfortunately, I\u2019ve come across several engineers that make the generalization error in the opposite direction: they state that single-ended circuits save current. I will present a counter-example that is sufficient to disprove this generalization. Keep in mind that it doesn\u2019t prove the opposite generalization (that differential circuits are always <\/em>better).<\/p>\n\n\n\n\n\n\n\n

Voltage-Mode Output<\/h2>\n\n\n\n

The two cases below assume that the dynamic range is limited by output voltage: that is, the circuit will clip its output and that determines the high-end of the dynamic range.<\/p>\n\n\n\n

Single-Ended Dynamic Range<\/h3>\n\n\n\n

Consider the single-ended CMOS amplifier shown below:<\/p>\n\n\n\n

\"\"<\/a><\/figure>\n\n\n\n

The output noise voltage is given by:<\/p>\n\n\n\n

$$ v_{n,o}^2 = \\frac{8kTg_m * |Z_L|^2}{3} $$<\/p>\n\n\n\n

$$ v_{n,o}^2 = \\frac{16 \\times kT * I_{DD} * |Z_L|^2}{3*V_{DSAT,N}} $$<\/p>\n\n\n\n

The maximum output voltage swing (zero-to-peak) is given by:<\/p>\n\n\n\n

$$ V_{o,max} = \\frac{V_{DD} – V_{DSAT,P} – V_{DSAT,N}}{2} $$<\/p>\n\n\n\n

The dynamic range is:<\/p>\n\n\n\n

$$ DR = \\frac{|V_{o,max}|^2}{v_{n,o}^2} = \\frac{(V_{DD} – V_{DSAT,P} – V_{DSAT,N})^2 \\times 3V_{DSAT,N}}{4 \\times 16kT \\times I_{DD} \\times |Z_L|^2} $$<\/p>\n\n\n\n

Differential Dynamic Range<\/h3>\n\n\n\n

Consider the differential CMOS amplifier:<\/p>\n\n\n\n

\"\"<\/a><\/figure>\n\n\n\n

The output noise voltage is given by (ID<\/sub> is the current in each side of the differential pair; it is half of IDD<\/sub>, the total current):<\/p>\n\n\n\n

$$ v_{n,o}^2 = \\frac{8kTg_m \\times|Z_L|^2}{3} = \\frac{16 \\times kT \\times I_{DD} \\times |Z_L|^2}{3*V_{DSAT,N}} $$<\/p>\n\n\n\n

The maximum output voltage swing (zero-to-peak) is given by:<\/p>\n\n\n\n

$$ V_{o,max} = V_{DD} – V_{DSAT,P} – V_{DSAT,N} – V_{DSAT,N2} $$<\/p>\n\n\n\n

The dynamic range is:<\/p>\n\n\n\n

$$ DR = \\frac{|V_{o,max}|^2}{v_{n,o}^2} = \\frac{4(V_{DD} – V_{DSAT,P} – V_{DSAT,N} – V_{DSAT,N2})^2 \\times 3V_{DSAT,N}}{4 \\times 16kT \\times I_{DD} \\times |Z_L|^2} $$<\/p>\n\n\n\n

Comparison<\/h3>\n\n\n\n

We see that the dynamic range is equivalent in both cases. The difference is the terms 4(VDD<\/sub> \u2013 VDSAT,P<\/sub> \u2013 VDSAT,N<\/sub> \u2013 VDSAT,N2<\/sub>) in the differential case versus (VDD<\/sub> \u2013 VDSAT,P<\/sub> \u2013 VDSAT,N<\/sub>) in the single-ended case. In many cases, the differential dynamic range is larger. In fact, as long as<\/p>\n\n\n\n

$$ V_{DSAT,N2} < \\frac{3}{4}(V_{DD} – V_{DSAT,P} – V_{DSAT,N}) $$.<\/p>\n\n\n\n

However, in the case where you can\u2019t meet this requirement, you can get rid of MN2<\/em> (albeit at the cost of common-mode rejection).<\/p>\n\n\n\n

Conclusion<\/h3>\n\n\n\n

We\u2019ve seen a case where the differential circuit shows more dynamic range than the single-ended counterpart. My guess is that most people who say that differential means more current don\u2019t realize that you don\u2019t have to have the same current in each branch of the differential circuit (you can split the current in half).<\/p>\n\n\n\n

One limitation of the above analysis is that I assume that the input voltage is available in a differential form, and that the output is consumable in its differential form. Obviously, if this isn\u2019t the case, the above analysis may or may not work. The case becomes more specific and the generalization fails.<\/p>\n\n\n\n

That said, I\u2019ve seen plenty of line-ups where a transformer\/balun is placed off-chip to convert the chip\u2019s inputs\/outputs to differential. Requiring differential I\/O at the chip level doesn\u2019t mean requiring differential I\/O at the board level.<\/p>\n\n\n\n

Current-Mode Output<\/h2>\n\n\n\n

I\u2019ve detailed the use of current-mode circuits<\/a> before. It\u2019s possible to treat this as a special case of the voltage-mode output analysis, with ZL<\/sub> being small. The only problem with that extrapolation is that if ZL<\/sub> is<\/em> small, the maximum swing probably won\u2019t be dictated by voltage: the circuit will slew way before it clips. As a result, instead of Vo,max<\/sub> being given by the previous equation, we have:<\/p>\n\n\n\n

Single-ended:<\/p>\n\n\n\n

$$V_{o,max} = \\frac{\\alpha \\times I_{DD} \\times |Z_L|}{2}$$<\/p>\n\n\n\n

Differential:<\/p>\n\n\n\n

$$V_{o,max} = \\alpha \\times I_{DD} \\times |Z_L|$$<\/p>\n\n\n\n

where \u03b1 is a factor that indicates what fraction of quiescent current can be used as signal current.<\/p>\n\n\n\n

The advantage is even more apparent: you\u2019re getting 4\u00d7 the dynamic range.<\/p>\n\n\n\n

Additional Benefits<\/h2>\n\n\n\n

In addition to the improved dynamic range (power-drain efficiency), differential circuits offer:<\/p>\n\n\n\n

  • Reduced susceptibility to supply noise: a good chunk of supply noise appears as common-mode, so a fully-differential circuit will reject (ignore) it<\/li>
  • Improved IM2: IM2 generally appears as common-mode and to a large amount gets rejected<\/li>
  • Reduce supply bounce (more beneficial for switch-mode circuits): since there\u2019s a complementary action at the nodes in the differential circuit, much less noise is induced on the supply during dynamic operation<\/li><\/ul>\n\n\n\n

    Disadvantages<\/h2>\n\n\n\n

    I can only point out a few disadvantages to the approaches presented here\u2013and they really have nothing to do with single-ended (versus differential) circuits:<\/p>\n\n\n\n

    • Common-mode feedback: you\u2019re generally going to need a common-mode feedback (and common-mode sensing). However, even the single-ended topology (shown above) requires some bias adjustment to set its output bias voltage. This is more of a property of CMOS design (high-impedance loads) than a trade-off of single-ended\/differential circuits.<\/li>
    • Lower swing: once again, this is a property of the differential pair. But, a lot of the differential benefit (common-mode rejection ratio) comes from using the differential pair.<\/li><\/ul>\n\n\n\n

      True disadvantages:<\/p>\n\n\n\n

      If you\u2019re using minimum-size devices, you end up spending twice the current with the differential circuit than with the single-ended version. However, when (in analog design), have you used minimum-sized devices?<\/p>\n\n\n\n

      The benefits of differential circuits occur when you get to analyze the noise and signal swing differentially. However, if the circuit you\u2019re driving doesn\u2019t respond to a differential input, the benefits aren\u2019t as great.<\/p>\n\n\n\n

      Conclusion<\/h2>\n\n\n\n

      It seems to me that most of the people that globally avoid differential circuits subscribe to the thought that since there are two current branches, there must be double the current. However, like I said above, this is only true if your branches are using minimum-sized devices. Otherwise, you can always split the device in half and distribute the same current across a differential pair.<\/p>\n\n\n\n

      <\/p>\n","protected":false},"excerpt":{"rendered":"

      Introduction From my personal blog: I\u2019ve been lucky enough to find myself in a team that\u2019s intent on finding the best circuit design for a given application. This doesn\u2019t happen often to many people, but I feel that I\u2019ve had more than my share of this opportunity. The conclusion is usually that we come up […]<\/p>\n","protected":false},"author":4,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[3],"tags":[147,149,61,85,148,59],"class_list":["post-753","post","type-post","status-publish","format-standard","hentry","category-analog-pro","tag-differential","tag-dynamic-range","tag-noise","tag-power","tag-single-ended","tag-snr"],"jetpack_featured_media_url":"","jetpack_shortlink":"https:\/\/wp.me\/poCEy-c9","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/753","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/comments?post=753"}],"version-history":[{"count":62,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/753\/revisions"}],"predecessor-version":[{"id":1159,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/posts\/753\/revisions\/1159"}],"wp:attachment":[{"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/media?parent=753"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/categories?post=753"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.circuitdesign.info\/blog\/wp-json\/wp\/v2\/tags?post=753"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}