Tag Archives: fully custom
MOS Diffusion Parasitics
I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance.
Posted in Analog Professional Also tagged CMOS, diffusion, high speed logic, layout, parasitics 1 Comment
You want latches? We got latches | Flip-Flop Design