I’ve received a request to detail the design of a flip-flop. Before I get to that, I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance.

First, here’s the schematic for an inverter and an associated diagram of the wafer structure. The wafer is drawn vertically to match the schematic:


The upper p+, gate and p+ form the PMOS device. The lower n+, gate and n+ form the NMOS device. The p+ and n+ diffusions in the center are tied together to form the output node. The gates of the devices are tied together to form the input node. Of course, this diagram of diffusions is a simplification. A more detailed diagram is shown below, with body (back-gate/bulk) connections shown:


This diagram is of a dual-well process. I am not considering the triple-well case for this discussion, since isolation isn’t the topic of this article. In this case, I have tied the body of the NMOS device (substrate) to ground (VSS), and the body of the PMOS device (N-Well) to supply (VDD). Each of these diffusions (p+ or n+) yield a diode between their respective nodes and the body connection.

Since the NMOS source is connected to VSS, and the body is also connected to VSS, this diode is shorted (anode and cathode both connected to VSS). Similarly, since the PMOS source is connected to VDD, and the body is also connected to VDD, this diode is shorted (anode and cathode both connected to VDD). In short, no signal travels through the source nodes of either device; the source node does not move and its diode is essentially irrelevant. Consequently, the equivalent circuit model can exclude these devices:


I have explicitly drawn the drain diffusion diodes. The novice circuit designer should beware that these diodes are typically contained in the MOS models and do not explicitly need to be added—although their parameters (area, perimeter) would need to be specified for accurate simulation.

Our final step is to consider the geometric effect of these diffusion areas. I have shown a single p+ diffusion enlarged below:


It is essentially a cube of p+ in the N-Well. There is a diode junction on every surface of this cube except the top:

  • The bottom of the cube has a diode area proportional to the width W length SD of the diffusion.
  • The front and back walls of this cube have a diode area proportional to HD and SD
  • The left and right walls have a diode area proportional to W and HD.

Now, imagine that this diffusion is the drain diffusion of a PMOS device. Imagine that the gate of the PMOS device is to the left of this diffusion. Then, the left sidewall doesn’t really have a diode to the body; it is instead modeled by the MOS device itself.

Typically, to specify this parasitic on a MOS model, one would specify the drain area (W x SD) and the perimeter (2xSD + W). From the perimiter, the sidewall area is computed automatically, since HD is a process parameter and does not vary from FET to FET.

The optimization becomes minimizing the area and perimeter for a given width W of FET. Consider the following FET:


It has a drain diffusion area of W & SD and a perimeter of 2SD + W, where SD is a design-rule parameter giving the minimum distance from gate edge to diffusion edge with enough space for a contact in the diffusion. If, instead, we share diffusions between two FET gates (by splitting up one device into two), we greatly reduce the perimeter and area per device width:

scan0110c - Copy For the same total width W, we get an area of W/2 x SD and a perimeter of just 2 x SD. One should note that the SD is once again the minimum diffusion length that can accommodate a contact. In some cases, the contact is not necessary. For example, in the case of a cascode, one can share a diffusion without placing a contact—since the shared diffusion does not need to be routed elsewhere:


Finally, in older processes, it may be possible to implement a “circular FET”:


This configuration has no perimeter (side-wall) capacitance on the drain diffusion, at the cost of perhaps slightly larger area (bottom surface) capacitance. Unfortunately, in modern processes, the geometries are so fine that the corners tend to be an issue: although they appear to have 45° angles, the inner corner tends to curve inward and form a true circle. This inward growth of the gate causes the effective gate length to suffer (larger gate length). Instead of having a 20% faster FET (simulations without the curved interior gate), one can see a 20% slower FET (actual on-silicon performance).

In the next post, I will show some flip-flop designs. Cosider a subscription via RSS or via email.