Tag Archives: layout
MOS Diffusion Parasitics
I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance.
Posted in Analog Professional Also tagged CMOS, diffusion, fully custom, high speed logic, parasitics 1 Comment
Pictorial introduction to using Cadence & Subversion
I previously blogged about some scripts I use to help Cadence & Subversion be more compatible. I received some feedback that the scripts were incomplete and came without any usage model. So, I went through an excercise to document the scripts and to make sure they were complete.
Posted in Analog Professional Also tagged analog, cadence, eda, integration, schematic, scripts, Skill, subversion, symbol, tutorial, version control Comments closed
Getting subversion and Cadence to play nice together
I wrote a set of scripts to make Cadence IC tools & Subversion work together. This requires subversion 1.4 or higher. Red Hat Enterprise Linux 4 by default ships with 1.3. See also Pictorial Introduction to Using Cadence/Subversion for detailed tutorial on usage. This post is mostly about the guts of the scripts. Note: this [...]
Posted in Analog Professional Also tagged cadence, eda, revision control, schematic, subversion, sybmol, version control 13 Comments
PCB & IC Layout Designer