Tag Archives: layout

PCB & IC Layout Designer

I generally don’t accept solicitations to post resumes, but I am making an exception for a very talented friend of mine. I know a very good IC designer and PCB designer. My experience with him is as an IC layout designer. However, most of his PCB customers cite him as the best PCB layout designer […]

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MOS Diffusion Parasitics

I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance.

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Pictorial introduction to using Cadence & Subversion

I previously blogged about some scripts I use to help Cadence & Subversion be more compatible. I received some feedback that the scripts were incomplete and came without any usage model. So, I went through an excercise to document the scripts and to make sure they were complete.

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Getting subversion and Cadence to play nice together

I wrote a set of scripts to make Cadence IC tools & Subversion work together. This requires subversion 1.4 or higher. Red Hat Enterprise Linux 4 by default ships with 1.3. See also Pictorial Introduction to Using Cadence/Subversion for detailed tutorial on usage. This post is mostly about the guts of the scripts. Note: this […]

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