Supply voltage, current, RF impedance, and CMOS scaling
Consider the circuit below: Let’s say that you’ve designed the circuit with a supply voltage (VDD) of 2.4 V. It’s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are: PMOS: IDP×VDSATP = […]