Categories
Email notification of new posts
Tag Archives: SNR
Supply voltage, current, RF impedance, and CMOS scaling
Consider the circuit below:
Let’s say that you’ve designed the circuit with a supply voltage (VDD) of 2.4 V. It’s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are:
PMOS: IDP×VDSATP = 10 mA×0.6 [...]
Posted in Analog Professional Also tagged CMOS, impedance, power, RF, scaling, SNR power, supply, voltage Leave a comment
Fundamentals of Analog/RF design: Noise, Signal, Power
Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog/RF design: that to maintain a given SNR, a certain amount of power must be consumed [...]
Calculation of ADC SNR in Cadence Skill/Ocean
However, here's how I compute SNR/SNDR from an FFT using Cadence Ocean/Skill.
Response to edaboard question “How can I deal with 3rd HD in a 2nd SigmaDelta Modulator”
In response to: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator
It’s possible that the OTA is limiting you. Doing a matlab model of the sigma-delta and running it should tell you whether it is a circuit problem or a system-level problem. My hunch is that it’s a system-level problem: the noise-shaping [...]
The benefits of differential circuits