Introduction From my personal blog: I’ve been lucky enough to find myself in a team that’s intent on finding the best circuit design for a given application. This doesn’t happen often to many people, but I feel that I’ve had more than my share of this opportunity. The conclusion is usually that we come up […]
Tag Archives: SNR
Consider the circuit below: Let’s say that you’ve designed the circuit with a supply voltage (VDD) of 2.4 V. It’s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are: PMOS: IDP×VDSATP = […]
Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog/RF design: that to maintain a given SNR, a certain amount of power must be consumed […]
However, here’s how I compute SNR/SNDR from an FFT using Cadence Ocean/Skill.
In response to: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator It’s possible that the OTA is limiting you. Doing a matlab model of the sigma-delta and running it should tell you whether it is a circuit problem or a system-level problem. My hunch is that it’s a system-level problem: the […]