Typical CMOS device/process options
I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let’s go over some process options that effect leakage.
I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let’s go over some process options that effect leakage.
In a previous post, I discussed the trade-offs in linearity of several continuous-time sigma-delta schemes. In this post, I will describe a method that linearizes the sigma-delta noise-shaping filter (NSF). That is, the scheme presented in this article greatly suppresses the linearity requirements on the noise-shaping filter. This method applies to both discrete-time and continuous-time […]
The continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) is a class of sigma-delta analog-to-digital converters that utilize a continuous-time noise-shaping filter (NSF | H(s)). In this post, I analyze a few noise-shaping filter (NSF) architectures that affect highly linear CTSD ADC’s.
I’ve decided to go through some basics of circuit design. In this post, I’ll cover the different types of circuit simulator analyses. Most are available in SPICE, Synopsys HSPICE, Cadence Spectre, and Agilent ADS, depending on vendor-specific options.
Consider the circuit below: Let’s say that you’ve designed the circuit with a supply voltage (VDD) of 2.4 V. It’s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are: PMOS: IDP×VDSATP = […]
Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog/RF design: that to maintain a given SNR, a certain amount of power must be consumed […]
In this post, I will show an evolution of a trans-conducting LNA (rather than a voltage-gain LNA). This is a prime example of current-mode circuit design, which has benefits in terms of linearity—especially for low-voltage scaling in RFCMOS design.