I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let’s go over some process options that effect leakage.
Typically, foundries offer a few variations of there processes. I will call them general purpose (GP) and low power (LP). They differ in what I call the core devices, after which a process is usually named—for example, CMOS090 (90 nm) or TSMC 0.18μm.
The GP represents the state of the art and usually drives large digital IC’s, including general purpose microprocessors and DSP’s. The traits of the GP process are a lower threshold and supply voltage, and possibly smaller effective gate length.
The LP is usually a variant of the GP process optimized to reduce leakage (at the expense of speed). The LP option is usually used for highly integrated analog & RF CMOS IC’s, such as radios (RF transceivers), ADC’s, etc. Typically, the LP allows for a slightly higher supply voltage and sometimes has a slightly larger effective gate length. However, the main trait of the LP process is that the threshold is increased a bit from the GP process to allow for lower leakage. I’m not entirely sure if the higher supply voltage and gate length are intentional or are a byproduct of the higher threshold.
Almost universally, all modern processes offer an “I/O” device. This is essentially a device from a prior process node (1.8 V, 2.5 V, or 3.3 V) with a larger gate length (0.18 um, 0.25 um, or 0.35 um). They are provided from a digital perspective as devices for pad drivers etc. However, they usually form the workhorse of analog/RF IC’s especially at baseband.
In both the GP and LP flavors, there are additional device options not necessarily universally, but usually:
- High-Vt: a core device with the threshold increased for lower leakage. This is also useful for larger output range on a diff pair—which depends on the input devices’ Vt—but usually an I/O device is even better.
- Low-Vt: a core device with the threshold decreased for higher performance (at the expense of leakage)
- Zero-Vt: a core device with a zero threshold voltage. This is useful for bypass switches and source followers.
These devices usually require additional mask steps and therefore incur additional processing costs.
Basically, to minimize leakage, one should use the device with the highest threshold voltage that gets the job done. In order of preference:
- I/O Device
- High-Vt core device (if it is already available or if the expense makes sense)
- Core (medium-Vt) devices
Of course, each of these options have the implicit tradeoff of performance/speed at the expense of leakage. What do you do when you want performance during active operation and low leakage during a standby mode? I will detail two methods in a future article.
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