Category Archives: Digital Professional

Posts that would interest digital (both fully custom digital and synthesized logic) designers.

Median vs Mean

I’ve been doing some statistical measurements lately (more to follow). It occurs to me that while most people measure the mean of a set of measurements, the median is more useful.

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Non-Radix-2 FFT in Cadence/Ocean/Skill/Spectre | Using Cadence IPC to talk to Matlab (or anything else)

Introduction I had been working on a pulse-width-modulation (PWM) design. It was a pseudo-digital implementation, in that the output was clocked by a high-speed clock. The actual switching rate was much lower than this clock. I wanted to simulate this design in Cadence/Spectre by running a transient and then taking an FFT. However, I ran […]

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You want latches? We got latches | Flip-Flop Design

The two inverters chasing their tail to the right of the input inverters represent a memory unit (i.e. a latch). When one output is high the other one is forced low. This low output then reinforces the first output being high. These two inverters form a positive feedback system.

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Minimizing leakage for high-performance CMOS circuits

I was asked a question on how to reduce leakage for digital circuits. I started by detailing process options that effect leakage, each effective both leakage and circuit performance. In this article, I will detail two methods to reduce leakage while maintaining circuit performance. I assume that the circuit at hand requires the highest performance […]

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Typical CMOS device/process options

I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let’s go over some process options that effect leakage.

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