Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog/RF design: that to maintain a given SNR, a certain amount of power **must** be consumed by an analog/RF circuit.

## Transconductors

### MOS Thermal Noise

Shown below is a disembodied MOS transconductor:

It takes an input voltage vi and outputs a current i_{o}. To avoid clipping, i_{o} would need to be less than I_{D}, the bias voltage on the MOS transistor. However, let’s say that for some linearity requirement (IM_{2}, IM_{3}, IM_{5}, etc.) that we limit i_{o} to be less than α×I_{D}.

So, we know the signal power is:

P_{sig} = (α×I_{D})^{2} = α^2×I_{D}^2

This power is computed as a current; we could equally have the transconductor drive a specified load impedance and compute all the quantities as voltage, but they will not change the end result.

Likewise, the noise current power is:

Pnoise = 8×k×T×g_{m}×B/3

At this point, it is useful to represent g_{m} in terms of voltage and current:

g_{m} = 2×I_{D}/V_{DSat}

→ P_{noise} = 16×k×T×I_{D}×B/(3×V_{DSat})

Therefore:

SNR = P_{sig}/P_{noise} = 3×α^2×I_{D}×V_{DSat}/(16×k×T×B)

Note that the term I_{D}×V_{DSat} is a lower-bound on the power dissipated across the FET. In fact, the actual power dissipated across the FET is I_{D}×V_{DS}, which is actually greater than I_{D}×V_{DSat}, since V_{DS} > V_{DS} to keep the FET in saturation.

To summarize:

- For a given SNR, we need a certain I
_{D}×V_{DSat}product (P_{min)} - The actual power dissipated by the FET is greater than this I
_{D}×V_{DSat}product P_{min} - Therefore, the SNR dictates how much power we must dissipate

### BJT Noise

A similar argument holds for the BJT. The difference is that the BJT’s are less sensitive to voltage, since due to their exponential current-voltage curve, the voltage varies very little:

P_{noise} = 2×k×T×B×I_{C}/V_{t}

P_{sig} = α^2×I_{C}^2

SNR = α^2×I_{C}×V_{t}/(2×k×T×B)

Once again, this I_{C}×V_{t} is a lower-bound on the noise dissipated across the BJT: V_{BE} > V_{t} and V_{CE} > V_{BE} → V_{CE} > V_{t}. The true power dissipated across the BJT is I_{C}×V_{CE} which is greater than Pmin = I_{C}×V_{t}, and to maintain a certain SNR, we have P_{min} = SNR×k×T×B/(α^2).

## Loads

### Resistor Noise

We now veer off into load country, considering resistor loads for our transconductor:

Considering only noise due to the resistor, and making the assumption that the signal current is once again limited to α×I_{D} (where I_{D} = I_{R}):

P_{noise} = 4×k×T×B/R = 4×k×T×B×I_{R}/V_{R}

SNR = α^2×I_{R}×V_{R}/(4×k&Times;T×B)

Note that this case is not general: in many cases, we don’t have to have I_{R} = I_{D}, so the P_{sig} has nothing to do with the resistor current. My intent is not to generalize to that much degree. I assume we have a transconductor–and every transconductor has to have a load (resistive, inductive, or active) that supplies dc current.

### Active Loads

Going through the math, one finds that active loads (BJT or MOS) also follow a similar derivation: the noise contributed by the load is proportional to the current to minimum-voltage ratio of the load. Also, the signal current coming into the load is constrained by the load current, since that same load current flows through the transconductor:

MOS Load: P_{noise} = 16×k×T×I_{D}×B/(3×V_{DSat}) | P_{sig} = α^2×I_{D}

BJT Load: P_{noise} = 2×k×T×B×I_{C}/V_{t} | P_{sig} = α^2×I_{C}

## Final Note

One final note: many times circuit designers think that they need to maximize g_{m} of devices to minimize noise. This optimum is not always the case. Generally, for a transconductor, better gm yields better SNR (assuming linearity is not an issue). However, the g_{m} of a load makes it add more (current) noise without improving signal power. Therefore, for loads, one wants to *minimize* g_{m}.

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