Author Archives: Poojan Wagh

You want latches? We got latches | Flip-Flop Design

The two inverters chasing their tail to the right of the input inverters represent a memory unit (i.e. a latch). When one output is high the other one is forced low. This low output then reinforces the first output being high. These two inverters form a positive feedback system.
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MOS Diffusion Parasitics

I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance.
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Minimizing leakage for high-performance CMOS circuits

I was asked a question on how to reduce leakage for digital circuits. I started by detailing process options that effect leakage, each effective both leakage and circuit performance. In this article, I will detail two methods to reduce leakage while maintaining circuit performance. I assume that the circuit at hand requires the highest performance [...]
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Typical CMOS device/process options

I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let’s go over some process options that effect leakage.
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Unity STF | A sigma-delta linearization method

In a previous post, I discussed the trade-offs in linearity of several continuous-time sigma-delta schemes. In this post, I will describe a method that linearizes the sigma-delta noise-shaping filter (NSF). That is, the scheme presented in this article greatly suppresses the linearity requirements on the noise-shaping filter. This method applies to both discrete-time and continuous-time [...]
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Continuous time sigma-delta ADC noise shaping filter circuit architectures

The continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) is a class of sigma-delta analog-to-digital converters that utilize a continuous-time noise-shaping filter (NSF | H(s)). In this post, I analyze a few noise-shaping filter (NSF) architectures that affect highly linear CTSD ADC’s.
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Circuit Simulator Analyses

I’ve decided to go through some basics of circuit design. In this post, I’ll cover the different types of circuit simulator analyses. Most are available in SPICE, Synopsys HSPICE, Cadence Spectre, and Agilent ADS, depending on vendor-specific options.
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Supply voltage, current, RF impedance, and CMOS scaling

Consider the circuit below: Let’s say that you’ve designed the circuit with a supply voltage (VDD) of 2.4 V. It’s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are: PMOS: IDP×VDSATP = [...]
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