Circuit Design | Tutorials and Insights in Electronics and Circuit Design

The Viterbi Sigma-Delta (at CircuitSage)

By Poojan Wagh | Published: January 12, 2009

I’ve posted a guest article at Circuit Sage, detailing the derivation of a “Viterbi” over-sampling data converter. I’m quite proud of this one. Go over and check it out.

FYI: this is also the reason I didn’t post directly to this site this week. I try to do a post per week, but the article at Circuit Sage took up most of my resources.

In case you’re wondering, I will continue to post primarily here. I decided to do the Circuit Sage post to drive more traffic here. My goal for this site is that it should make up for hosting fees. It’s nowhere there now, and maybe it’s unrealisted to expect that from Google AdSense. But, it’s worth trying.

Posted in Analog Professional | Tagged CircuitSage, data converter, Delta Sigma, oversampling, sigma delta, Viterbi | Leave a comment

Asymmetric chopping for improved IM3 | A dead-end research topic?

By Poojan Wagh | Published: January 5, 2009

In my prior post, I discussed the use of “chopping” (or pre- and post-mixing) to improve the IM2 of RF/analog circuits. New readers should go back and read that post in order to understand the nomenclature and variable names in this post.

Lately, I’ve been considering whether any similar (but different) technique can be used to improve IM3. I went through a few thought experiments and eventually concluded that it couldn’t be done. Nonetheless, I was quite proud of the journey and thought it was worth sharing. I also hope that someone else will use the ideas presented here to come up with something better. (This hope is true of everything I publish here.)

In short, it’s good to celebrate your achievements and document your failures. This post is a case of the latter.

Posted in Analog Professional | Tagged chopping, IIP2, IIP3, IM2, IM3 | 6 Comments

Reader Round-Up (vol 1)

By Poojan Wagh | Published: December 28, 2008

I’ve been receiving a few questions from the readers. (Yes, I actually have readers—other than you.)

2008-12-28 Update

I misread the email; the initial version of the I/Q noise figure discussion was completely wrong.

Posted in Analog Professional | Tagged cadence, downconverter, noise figure, quadrature, spectre, stability | Leave a comment

Chopping to alleviate IM2,

By Poojan Wagh | Published: December 20, 2008

IM2

Consider the fully differential amplifier shown below:

Posted in Analog Professional | Tagged chopping, IM2, IP2, matching, mixer, pseudonoise, spread spectrum | 3 Comments

You want latches? We got latches | Flip-Flop Design

By Poojan Wagh | Published: December 14, 2008

I received a request to go through the design of a flip-flop. Every flip-flop I have designed has been a master-slave D flip-flop, built out of two D latches. I’ll start with a basic CMOS latch and go into more optimized latch topologies.

Update 2008-12-19

This post probably didn’t make sense to many of you. I was representing C-bar (negation of C) by an underline. Unfortunately, WordPress (or maybe my theme) wasn’t rendering this underline, so $$\overline{C}$$ didn’t look any different from $$C$$. I’ve (obviously) rectified this ambiguity through the magic of Latex. If there are any errors now, they are solely my fault. (Let me know.)

Posted in Digital Professional | Tagged CMOS, divider, fully custom, memory | 7 Comments

MOS Diffusion Parasitics

By Poojan Wagh | Published: December 9, 2008

I’ve received a request to detail the design of a flip-flop. Before I get to that, I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance. Read More »

Posted in Analog Professional | Tagged CMOS, diffusion, fully custom, high speed logic, layout, parasitics | 1 Comment

Minimizing leakage for high-performance CMOS circuits

By Poojan Wagh | Published: December 2, 2008

I was asked a question on how to reduce leakage for digital circuits. I started by detailing process options that effect leakage, each effective both leakage and circuit performance. In this article, I will detail two methods to reduce leakage while maintaining circuit performance. I assume that the circuit at hand requires the highest performance in some active mode but must greatly reduce its leakage in a standby mode. Read More »

Posted in Digital Professional | Tagged body bias, leakage, regulator, submicron | 5 Comments

Typical CMOS device/process options

By Poojan Wagh | Published: November 29, 2008

I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let’s go over some process options that effect leakage. Read More »

Posted in Digital Professional | 1 Comment

Tutorials and Insights in Electronics and Circuit Design