PCB & IC Layout Designer

I generally don’t accept solicitations to post resumes, but I am making an exception for a very talented friend of mine.

I know a very good IC designer and PCB designer. My experience with him is as an IC layout designer. However, most of his PCB customers cite him as the best PCB layout designer they’ve come across. I’ll focus on his IC skills, since I can attest to that.

He’s most often hired as a consultant embedded in a design team. However, he’s capable of and set up for turn-key work (taking schematics and sending back GDS II). He’s skilled in Cadence (Virtuoso XL, Assura) and Mentor (IC Layout, Calibre) design tools.

If you’re interested, fill out the Feedback (Contact Us) form. I will forward requests to him.

He’s worked on the following products (since I’ve met him) and much more:

  • CMOS 90 nm transceiver IC including ADC/DAC, RF: massive integration effort, requiring careful shielding and differential matching of many RF/analog lines
  • IBM 8WL BiCMOS IC including high-linearity mixer with feedback: extremely compact layout, minimizing RF parasitics
  • CMOS 90 nm continuous-time sigma-delta ADC: detailed matching (common centroiding) of CMOS devices and matching of routing parasitics
  • TSMC 0.18 um CMOS class-D audio amplifier IC: integration and isolation of several analog blocks with large digital circuit
  • CMOS 0.18 um all-digital RF transmitter (resulted in this publication)

Each of the above has been a first-pass success. He contracted for over a decade at Motorola Labs (Motorola’s corporate research center at their headquarters near Chicago), Atmel, Freescale Semiconductor, and several Motorola product groups. He ran a circuit board development group at Tellabs. He’s extremely pleasant to work with and does very well in a team environment (both as a lead developer and as a team member).

He is a US citizen.

He is available for hourly contracting.

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Polar vs Cartesian RF Modulator Efficiency

I’ve been fielding quite a few questions lately about polar modulation. Indeed, polar modulators are theoretically more efficient. However, this does not need to be the case. I will highlight (technically, self-promote) a Cartesian scheme that can produce an RF signal as efficiently as a polar modulator—with fewer implementation issues.
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Dual DAC CTSD | Wider Bandwidth and Higher SNR — Part 2


So, we want to break down our continuous-time sigma-delta feedback into two paths:

  1. A low-precision tight loop that delivers the first sample to the quantizer
  2. A higher-precision loop that goes through a clock delay to minimize “metastability” (indecision)

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Dual DAC CTSD | Wider Bandwidth and Higher SNR — Part 1


Consider our usual continuous-time sigma-delta (CTSD) ADC:

x(t) is the analog input and y[n] is the digital output and feedback signal that drives the DAC. H(s) is the loop filter and Q represents the quantizer.

One of the main difficulties with continuous-time sigma-delta’s is that when the digital output does not match the analog feedback, an error is created. This condition occurs when a very weak signal appears at the quantizer input, causing the quantizer to eventually go to +1 or -1 but to do so in a very slow and almost idle manner.
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Impulse Invariant Transform


The impulse invariant transform (IIT) is a method of taking a continuous-time system H(s) and converting it to a discrete-time system. There are multiple ways of doing this, but the IIT does so with the constraint that the impulse response of the discrete-time system is a sampled version of the impulse response of the continuous-time system.

Here’s an illustration:

…gets converted to…

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Non-Radix-2 FFT in Cadence/Ocean/Skill/Spectre | Using Cadence IPC to talk to Matlab (or anything else)


I had been working on a pulse-width-modulation (PWM) design. It was a pseudo-digital implementation, in that the output was clocked by a high-speed clock. The actual switching rate was much lower than this clock. I wanted to simulate this design in Cadence/Spectre by running a transient and then taking an FFT.

However, I ran into a bit of a snag: the quantization clock and my input clock rates were defined by the design, and they weren’t up to me. Moreover, these weren’t related by a power of 2. Unfortunately, Cadence Ocean (Skill) commands only allow for a radix-2 (power of 2 length) FFT. So, I was stuck. I needed a way to do a non-radix-2 FFT in Cadence. Here’s how I solved it using Matlab and getting Cadence and Matlab to talk (in a limited fashion).

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The Viterbi Sigma-Delta (at CircuitSage)

I’ve posted a guest article at Circuit Sage, detailing the derivation of a “Viterbi” over-sampling data converter. I’m quite proud of this one. Go over and check it out.movie Mechanic: Resurrection 2016 streaming

FYI: this is also the reason I didn’t post directly to this site this week. I try to do a post per week, but the article at Circuit Sage took up most of my resources.

In case you’re wondering, I will continue to post primarily here. I decided to do the Circuit Sage post to drive more traffic here. My goal for this site is that it should make up for hosting fees. It’s nowhere there now, and maybe it’s unrealisted to expect that from Google AdSense. But, it’s worth trying.

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Asymmetric chopping for improved IM3 | A dead-end research topic?

In my prior post, I discussed the use of “chopping” (or pre- and post-mixing) to improve the IM2 of RF/analog circuits. New readers should go back and read that post in order to understand the nomenclature and variable names in this post.

Lately, I’ve been considering whether any similar (but different) technique can be used to improve IM3. I went through a few thought experiments and eventually concluded that it couldn’t be done. Nonetheless, I was quite proud of the journey and thought it was worth sharing. I also hope that someone else will use the ideas presented here to come up with something better. (This hope is true of everything I publish here.)

In short, it’s good to celebrate your achievements and document your failures. This post is a case of the latter.

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