I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance.
Category Archives: Analog Professional
MOS Diffusion Parasitics
Posted in Analog Professional Tagged CMOS, diffusion, fully custom, high speed logic, layout, parasitics 1 Comment
Unity STF | A sigma-delta linearization method
In a previous post, I discussed the trade-offs in linearity of several continuous-time sigma-delta schemes. In this post, I will describe a method that linearizes the sigma-delta noise-shaping filter (NSF). That is, the scheme presented in this article greatly suppresses the linearity requirements on the noise-shaping filter. This method applies to both discrete-time and continuous-time [...]
Posted in Analog Professional Tagged continuous time, continuous time sigma-delta, linearity, sigma delta Leave a comment
Continuous time sigma-delta ADC noise shaping filter circuit architectures
The continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) is a class of sigma-delta analog-to-digital converters that utilize a continuous-time noise-shaping filter (NSF | H(s)). In this post, I analyze a few noise-shaping filter (NSF) architectures that affect highly linear CTSD ADC’s.
Posted in Analog Professional Tagged active RC, ADC, continuous time, Gm-C, linearity, noise shaping filter, sigma delta 5 Comments
Circuit Simulator Analyses
I’ve decided to go through some basics of circuit design. In this post, I’ll cover the different types of circuit simulator analyses. Most are available in SPICE, Synopsys HSPICE, Cadence Spectre, and Agilent ADS, depending on vendor-specific options.
Posted in Analog Professional Tagged ac, analysis, dc, harmonic balance, hbnoise, Noise, op, pnoise, pnoisehb, pss, steady, transient 3 Comments
Supply voltage, current, RF impedance, and CMOS scaling
Consider the circuit below: Let’s say that you’ve designed the circuit with a supply voltage (VDD) of 2.4 V. It’s performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are: PMOS: IDP×VDSATP = [...]
Fundamentals of Analog/RF design: Noise, Signal, Power
Analog design does not scale the way digital design does. Namely, as process shrinks, one does not immediately benefit by having reduced power consumption for the same performance. I will show in this post the main constraint involved in analog/RF design: that to maintain a given SNR, a certain amount of power must be consumed [...]
The case for the trans-conducting LNA
In this post, I will show an evolution of a trans-conducting LNA (rather than a voltage-gain LNA). This is a prime example of current-mode circuit design, which has benefits in terms of linearity—especially for low-voltage scaling in RFCMOS design.
Posted in Analog Professional 3 Comments
A compact common-mode feedback loop | using a PMOS triode device for CMFB
One of the defining traits of analog CMOS designers is the ability to implement a common-mode feedback (CMFB) loop. When the input devices on a differential pair are all NMOS (or NPN), and the loads are either inductors or resistors, a common-mode feedback loop is unnecessary, because the output resistance of the differential pair is [...]
Posted in Analog Professional Tagged bias, CMOS, common mode, continuous time, feedback, load, loop, opamp, OTA, stability 5 Comments