Reader Round-Up (vol 1)

I’ve been receiving a few questions from the readers. (Yes, I actually have readers—other than you.)

2008-12-28 Update

I misread the email; the initial version of the I/Q noise figure discussion was completely wrong.

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Chopping to alleviate IM2,

IM2

Consider the fully differential amplifier shown below:
scan0125

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You want latches? We got latches | Flip-Flop Design

I received a request to go through the design of a flip-flop. Every flip-flop I have designed has been a master-slave D flip-flop, built out of two D latches. I’ll start with a basic CMOS latch and go into more optimized latch topologies.

Update 2008-12-19

This post probably didn’t make sense to many of you. I was representing C-bar (negation of C) by and underline. Unfortunately, WordPress (or maybe my theme) wasn’t rendering this underline, so $$overline{C}$$ didn’t look any different from $$C$$. I’ve (obviously) rectified this ambiguity through the magic of Latex. If there are any errors now, they are solely my fault. (Let me know.)

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MOS Diffusion Parasitics

I’ve received a request to detail the design of a flip-flop. Before I get to that, I wanted to go through a bit of illustration with regard to minimizing MOS diffusion parasitics. I will start with the basics of detailing the MOS semiconductor structure. From there, I’ll display some layout configurations that minimize MOS diffusion capacitance. Read More

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Minimizing leakage for high-performance CMOS circuits

I was asked a question on how to reduce leakage for digital circuits. I started by detailing process options that effect leakage, each effective both leakage and circuit performance. In this article, I will detail two methods to reduce leakage while maintaining circuit performance. I assume that the circuit at hand requires the highest performance in some active mode but must greatly reduce its leakage in a standby mode. Read More

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Typical CMOS device/process options

I received an inquiry on how to reduce leakage. I will cover how to do so in a future article. However, before I do, let’s go over some process options that effect leakage. Read More

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Unity STF | A sigma-delta linearization method

In a previous post, I discussed the trade-offs in linearity of several continuous-time sigma-delta schemes. In this post, I will describe a method that linearizes the sigma-delta noise-shaping filter (NSF). That is, the scheme presented in this article greatly suppresses the linearity requirements on the noise-shaping filter. This method applies to both discrete-time and continuous-time sigma-delta ADC’s. However, it is more powerful with continuous-time sigma-delta because it enables the active-RC configuration.

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Continuous time sigma-delta ADC noise shaping filter circuit architectures

The continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) is a class of sigma-delta analog-to-digital converters that utilize a continuous-time noise-shaping filter (NSF | H(s)). In this post, I analyze a few noise-shaping filter (NSF) architectures that affect highly linear CTSD ADC’s.

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